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This paper presents detailed analysis of edge based NRZ equalizer proposed in IEEE 802.3ap Task Force. Paradox on spectrum zero at Nyquist frequency is explained. Design methods are improved. Optimization methods are proposed. Results at 10-Gb/s transmission through 2 practical backplanes verify the analysis, design, and optimization methods.
This paper proposes an optimization method for transmitter equalizers for high speed serial data transmission through lossy backplane channels. Detailed analytical analysis of transmitter equalizer design is carried out on the basis of variable tap spacing finite impulse response (FIR) filter. Results on a highly lossy 40-inch FR4 backplane channel are compared and discussed.
This paper presents an improved equalization circuit, with a linear equalizer (LE) and a decision feedback equalizer (DFE) in the receiver, for 10-Gb/s high-speed serial data transmission over highly lossy electrical backplane channels. Although DFE provides an effective way to compensate various channel impairments, the pre-cursor inter-symbol interference (ISI) is still a significant problem for...
This paper presents a programmable pre-cursor ISI equalization circuit for high-speed serial data transmission over highly lossy electrical backplane channels. Although decision-feedback-equalizer (DFE) provides an effective way to compensate various channel impairments, such as frequency dependent loss, dispersion and reflections in the legacy backplane environment, for high-speed, highly lossy band-limited...
This paper presents a 10-Gb/s backplane transmitter with a finite impulse response (FIR) pre-emphasis equalizer to suppress inter-symbol-interference (ISI) at data centers and transition edges simultaneously. The design concepts are discussed. Circuits in 0.13mum IBM CMOS technologies are given. Comparison with conventional data center oriented equalizer and transition edge oriented equalizer are...
This paper presents an integrated modeling, simulation and analysis technique for high-speed serial link transceiver over band-limited channel. The Verilog-A behavioral modeling blocks, transistor-level circuits based on the BSIM models, and the backplane channel with .s4p format model were simulated simultaneously in Cadence Spectre environment. The output data were post-processed with Matlab for...
A number of simulation methods dealing with measured S-parameters have been developed for the simulation of high-speed backplane transceivers and printed circuit board signal integrity analysis. Although these methods implemented in many circuit simulators provide correct system-level and transistor-level simulations, they usually fail to give correct results for many challenging backplane channels...
Wireline transceivers for high-speed data transmission through backplane and ethernet cables are important applications for microelectronic and nanoelectronic CMOS technologies. Although many circuit simulators provide correct system-level and transistor-level simulations, they usually fail to give correct results for many highly lossy or/and highly dispersive channels. This paper discusses the advanced...
This paper presents a novel CMOS edge equalizer for 10-Gb/s transceivers for backplane channels with high loss. The equalizer reduces ISI at edges and ISI at data centers simultaneously without incurring multilevel detection. Unlike conventional edge equalizer that recovers data from current sample and previous sample, this equalizer recovers data only from current sample so that error propagation...
This paper presents a decision-feedback-equalizer for 10-Gb/s backplane transceivers for highly lossy channels. Forward equalization is not used in order to avoid noise enhancement. The sampling phase is optimized to achieve maximum signal-to-noise-ratio at the sampling instants. The coefficients of feedback finite-impulse-response filter and the gain of variable-gain-amplifier are obtained automatically...
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