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When on-chip interconnection network scales to integrate more processing elements, the average end-to-end latency is highly increased due to long average hop distance. Though it has been discovered that, almost of the communication in large scale networks is between nodes in a short range, it revealed that the small portion of data delivery between distant nodes consumes or occupies most of the network...
In order to ease the communication cost, application tasks are always distributed to nearby nodes in NoC-enabled SoCs, which result in concentrated area of traffic and power distribution. To utilize the intellectual properties on a single chip, and at the meantime, to reduce the high latency due to the long routing hops in large scale on-chip networks, hierarchy has been adopted to provide more attractive...
This paper studies the implementation and optimization of a high-order weighted essentially non-oscillatory (WENO) solver to the solution of the Euler equations on the multi-core and many-core architectures (Intel Ivy Bridge CPU, Intel Xeon Phi 7110P coprocessor and NVIDIA Kepler K20c GPU). The implementation of up to ninth-order accurate WENO schemes is used in the solver. For the GPU platform, both...
Finite-time Lyapunov exponent (FTLE) is widely used to extract coherent structure of unsteady flow. However, the calculation of FTLE can be highly time-consuming, which greatly limits the application's performance efficiency. In this paper, we accelerate a double precision PDE-based FTLE application for two- and three-dimensional analytical flow field on Intel multi-core and many-core architectures...
To bridge the widening gap between computation requirements of terascale application and communication efficiency faced by gigascale multi-processor system-on-chip devices, a new on-chip communication system, dubbed Wireless Network-on-Chip (WNoC), has been proposed. This work centers on the design of a high-efficient, low-cost, deadlock-free routing scheme for domain-specific irregular mesh WNoCs...
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