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Summary form only given. While innovation in manufacturing continues to push the envelope of CMOS device scaling toward the physical limit, at the meantime, system integration has found an alternative path to delay the limitation by using silicon-interposer based design with through-silicon-via (TSV) or true 3-D IC die stacking to cram more devices within the same chip pacakge. These solutions enable...
The authors describe a 200-MHz PLL (phase-locked loop) in a 2- mu m CMOS technology employing an untrimmed current-controlled ring oscillator (CCO). Two phase detectors are included: a phase-frequency detector (PFD) for fast acquisition during data preamble (100% pulse density), and a mixer phase detector to lock on actual data (in the presence of missing pulses). Simulation results and experimental...
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