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Chip-package interaction has become a major concern due to increasingly porous low-K dielectrics. During the packaging process, shear stresses are exerted on fragile interconnect structures. We use a microprobe metrology system to experimentally measure how interconnect stacks with different dielectric porosities behave under various shear loading conditions and a wide range of temperatures.
We address package-induced degradation of BEOL interconnects and approaches for recovery. For dielectrics, we cover process options and position in stack for ULK films and how these lead to differences in strength. Experiments were designed to cross-compare multiple methods to test susceptibility of BEOL interconnect to CPI damage. We also address how Chip Package Interaction changes as BEOL features...
Miniaturization and increasing functional integration as the electronic industry drives push the development of feature sizes down to the nanometer range. Moreover, harsh operational conditions and new porous or nano-particle filled materials introduced on both chip and package level - low-k and ultra low-k materials in Back-end of line (BEoL) layers of advanced CMOS technologies, in particular -...
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