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At mm-wave frequency, the layout of CMOS transistors has a larger effect on the device performance than ever before in low frequency. In this work, the distance between the gate and drain contact (Dgd) has been enlarged to obtain a better maximum available gain (MAG). A 0.6 dB MAG improvement is realized when Dgd changes from 60 nm to 200 nm. By using the asymmetric-layout transistor, a four-stage...
This paper presents a 20-GHz pseudo-differential power amplifier (PA) fabricated in a standard 90-nm Si-CMOS process. The pseudo-differential PA has a two-stage cascode configuration with differential input and output ports. Assuming the use of an off-chip transformer, the input impedance of each single PA is designed to be 6.25 Omega and the output impedance to be 25 Omega. The individual amplifier...
In this paper, a three-stage LNA employing a dual noise-matching topology has been proposed. The proposed LNA has two noise-matched CS amplifiers in the first and second stages instead of the conventional cascode configuration, and the LNA realizes lower noise figure than the conventional one. The simulation results of the proposed LNA show that an input matching and output matching result less than...
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