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This paper presents a detailed study of SOI source/drain embedded SiGe (eSiGe) technology with a focus on parasitic characteristics. It shows that eSiGe can appreciably suppress on-state floating body effect and improve device exterior resistance. Although eSiGe only physically addresses P-FET, junction capacitances of both P- and N-FETs can be impacted.
This paper investigates the possibility of reducing the deposition temperature of silicon-germanium (Si1-xGex) thin films to 210degC and tuning the physical properties of the film locally to achieve optimal mechanical and electrical properties that are suitable for a wide range of microelectromechanical systems that can be postprocessed on top of standard prefabricated electronics or onto more exotic...
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