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In this presentation we review the evolution of radio access networks and introduce 5G, based on the current plans and expectations, as reported in the recent series of the Ericsson Mobility Reports. Standardization is an on-going effort, and much industry research is devoted to finding a good match of requirements — balancing system performance, flexibility and implementation imphcations. We present...
The thermal diffusivity of silicon DSi has been used to realize fully-CMOS frequency references. However, due to the temperature dependence of Dg, the accuracy of such frequency references is limited to about 1000 ppm (−55 °C to 125 °C, one-point trim) due to the inaccuracy of the on-chip temperature compensation circuitry. As an alternative, we propose a frequency reference based on the thermal diffusivity...
A compact differential voltage reference cell, which combines an original switched capacitor integrator with a digitally programmable bandgap core, is presented. The two-stage integrator maintains an always-valid output voltage while performing correlated double sampling to effectively reduce the effects of offset and flicker noise. Measurements performed on a prototype designed with the UMC 0.18...
This paper presents a constant with temperature (CWT) voltage reference generator (VRG) that utilizes only regular transistors in standard CMOS technology. By operating an NMOS transistor as a self-biased current source driving a diode-connected PMOS transistor in the subthreshold region, a sub-pW, temperature stabilized voltage can be generated. To improve line regulation, a self-regulation NMOS...
A 1.02nW current reference is designed with only PMOS transistors, thereby providing inherently low process variation and enabling trim-free operation. Thirty-two measured chips from 5 corner wafers in 180nm CMOS technology show an untrimmed within-wafer spread (σ/μ) of 1.6% and across-corner wafer-to-wafer spread of ±4.7%. The measured average temperature coefficient is 282ppm/°C from −40°C to 120°C...
A low-noise readout interface integrated with an antenna-coupled FET-based terahertz (THz) detector is designed and fabricated in a 0.15-μm CMOS standard technology. The implemented readout includes a cascade of a preamplification noise reduction stage based on a parametric chopper amplifier, and a direct analog-to-digital conversion by means of an incremental ΣΔ converter, substituting the lock-in...
A wideband auxiliary receiver embeds a band-reject N-path filter in the low-noise amplifier to improve the compression point. The receiver has high input impedance and it can be placed at the transmitter output without loading effects. Implemented in a 28nm CMOS technology it occupies 0.12mm2 active area and it can withstand up to +4 dBm QPSK modulated 20 MHz signal with less than 1-dB noise degradation...
A 300 MHz-12 GHz HBT-based mixer-first receiver in 130 nm BiCMOS is presented. The mixer core is composed of four SiGe HBTs driven by quadrature LO pulses with a shared emitter RF input and feedback from the baseband to HBT bases to generate baseband-to-RF impedance-transparency. This is analogous to effects seen in CMOS passive-mixer-first receivers, but at higher frequencies than attainable with...
A 402–405 MHz MICS-band wake-up receiver is presented that achieves −63.8 dBm sensitivity at 4.5 nW. High sensitivity at 400 MHz is accomplished via an 18.5 dB passive voltage gain transformer filter loaded by a high input impedance (Rin > 30 kΩ), high scaling factor (kED > 300), 1.8 nW current re-use pseudo-balun envelope detector, while low power is achieved by operating all active circuits,...
We present a cross-correlator ASIC for synthetic aperture imaging of Earth's atmosphere. Reconfigurability as a 2-level 96-channel or 3-level 48-channel cross-correlator provides adaptability to a wider array of applications. Implemented in a 65-nm CMOS process, the cross-correlator is capable of running at clock speeds of up to 3 GHz. In 2-level 96-channel mode, the cross-correlator consumes only...
This paper introduces an accuracy/energy-flexible configurable 2D Gabor filter based on stochastic computation, where bit streams representing information are used. The Gabor filters show a powerful feature extraction capability, but the calculation based on binary computation is complicated. As opposed to traditional memory-based methods that use fixed Gabor coefficients calculated by software in...
This paper presents an ultra-low energy and compact Fast Fourier Transform (FFT) processor suitable for pervasive sensing systems. To achieve high energy efficiency and small area, we design area-efficient memory-based architecture and equip it with two proposed techniques: (i) spatiotemporally finegrained active leakage suppression for sub-threshold voltage (sub-VTH) combinational logic and (ii)...
The paper demonstrates improved power side channel attack (PSCA) resistance of a 128-bit AES engine in 130nm CMOS using random fast voltage dithering (RFVD) enabled by integrated inductive voltage regulator (IVR) and all-digital clock modulation (ADCM). The measured power signatures at AES and IVR supply nodes show 9× reduction in peak test vector leakage assessment (TVLA) metric while also protecting...
This paper presents CMOS monolithic PPG sensor with distributed 1b delta-sigma light-to-digital convertor (LDC). Proposed unbiased photodiode (PD) based circuit with fully integrated PD in the same die efficiently performs direct light to digital conversion, and the distributed architecture further improves the dynamic range. The implemented sensor, fabricated in standard 0.18μm CMOS process, achieves...
A solid state 3D scanner based on a pulsed laser diode source and narrow time gating of a 2D CMOS single photon avalanche diode (SPAD) detector array is presented. The imager uses an on-chip delay-locked loop to program the time gating of 40 sub-arrays individually. The prototype detector has 80 × 25 pixels with a fill factor of 32 % in the sensor area. The chip has been fabricated in a 0.35 μm high-voltage...
Vision of patients with retinal implants is diminished by spatial lowpass behaviour of the interface between electrode and stimulated cells. Spatial highpass filtering can compensate the interface lowpass to a certain degree and thus improve visual perception. The retinal implant consists of an array of photodiodes, each with an amplification circuit and an electrode. The proposed spatial highpass...
A sun sensor implemented with a spiking pixel matrix is reported. It is the very first one based on an asynchronous event-based pixel array. A paradigm associated to classic digital sun sensors is solved with this approach. Only pixels illuminated by the sun light are readout. Hence, the output data flow is quite reduced. The computational load to resolve the sun position is quite low, comparing to...
A dynamic bias pre-amplifier based latch type comparator is designed in a 65nm CMOS process. Its performance is compared with the double-tail latch-type comparator fabricated on the same chip in terms of energy consumption, input referred noise and speed. Measurements demonstrate that the proposed dynamic bias pre-amplifier based comparator consumes 2.8 times less energy per comparator operation with...
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