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This paper discusses the priority issues on the energy infrastructure before and after the Great East Japan Earthquake in Japan. For the issue before the earthquake “Development and implementation of technologies that realizes a co-existence between sustainability and living comfortableness,” seven technologies are explained, such as “Improvement of efficiency in Energy use” including “Improvement...
This paper elaborates on the requirements of electricity grids when large amounts of regenerative energies, in particular from wind and solar power plants, have to be integrated. It shows the essential role of advanced power electronics for the de-carbonization of our energy supply.
Three basic intermediate bus architectures are reviewed for electronic power system developers. Salient features for practical system development are then discussed in detail, including power efficiency, regulation, component selection, load cross regulation, and board thermal flux density. The double regulated intermediate bus architecture has the best overall efficiency, regulation, size, and thermal...
A trench shielded planar gate IGBT is proposed in this paper. The unique 3D top cell structure, combining high density trench and low channel density, offers an excellent conduction vs. switching loss trade-off and a significantly better Short-circuit SOA compared to trench IEGTs. Measurements on fabricated devices show a 0.1V lower VCESAT for the same Eoff, and a 2x improvement in short circuit SOA.
Novel 3.3-kV trench IGBT with low loss and low dvAK/dt noise was developed. The structural feature of the IGBTs is deep p-WELL layers separated from trench gates. This structure suppresses excess VGE overshoot and then reduces recovery dvAK/dt. Moreover, this effect is enhanced by reducing the resistance of the deep p-WELL layers (RFP). It was found that, for the first time, the trade-off characteristics...
We proposed a PNM-IGBT [1] that can realize performance close to the theoretical limit shown by Nakagawa, et, al [2, 3]. In that work, we confirmed PNM-IGBT can achieve a very low saturation voltage due to its great injection enhancement effect. However, it is accompanied by a slight increase in turn-off-loss. We believe that we can diminish this increase by our unique control technique. Therefore,...
In this paper, a balanced High Voltage (HV) IGBT is presented. The proposed HV IGBT is composed of three technologies: Wide Cell Pitch CSTBTTM(III) for cell structure, Partial P collector utilizing LPT(II) buffer for vertical structure, and a novel area-efficient edge termination design. We called the above edge termination design “Linearly-narrowed Field Limiting Ring (LNFLR)”. The experiment results...
A 4H-SiC trench MOSFET has been developed that features the use of trench gates with a thick oxide layer on the bottoms of the trenches for relieving the electric field strength of the gate oxide layer. The maximum electric field strength and gate-drain charge (Qgd) of this device is 46% and 38% lower than that of a conventional MOSFET, respectively. A □5mm chip was fabricated with a thick oxide layer...
In this paper, we report our recently developed 2nd Generation, large-area (56 mm2 with an active conducting area of 40 mm2) 4H-SiC DMOSFET, which can reliably block 1600 V with very low leakage current under a gate-bias (VG) of 0 V at temperatures up to 200°C. The device also exhibits a low on-resistance (RON) of 12.4 mΩ at 150 A and VG of 20 V. DC and dynamic switching characteristics of the SiC...
We developed a new backside contact formation process for SiC power devices based on pulsed laser annealing providing an ohmic contact with lower contact resistance and better adhesion properties than contacts formed by conventional rapid thermal annealing. This process does not add any significant thermal budget to the wafer front side and therefore allows a “short thin wafer” process, means completing...
The threshold voltage of 4H-SiC MOSFET increases drastically by performing wet oxidation after nitridation of gate oxide without significant decrease in the channel effective mobility. The increment of the threshold voltage depends on the wet oxidation conditions, and wet oxidation improves the trade-off between the threshold voltage and the specific on-resistance. We fabricated 600 V 4H-SiC MOSFETs...
Vertical diodes with breakdown voltages up to 2.6kV have been fabricated on bulk GaN substrates. The measured figures-of-merit of these devices show performance near the theoretical limit of GaN. These vertical GaN diodes exhibit robust avalanche breakdown behavior with a positive temperature coefficient. System-level performance advantages have been demonstrated in power conversion applications....
A gate driver IC with programmable output resistance (Rout) capable of performing current balancing for parallel connected IGBTs is presented in this paper. This novel method is to dynamically adjust the gate driver Rout to minimize the difference in the turn-on/off delay times between parallel connected IGBTs. The programmable gate driver Rout is implemented using a segmented output stage technique...
In this paper, a novel 3D TSV (Through-Silicon-Via) transformer technology for power system-on-chip applications is proposed and demonstrated experimentally. The transformer used in the power system features a galvanic isolation of > 4 kV and a voltage gain of > −3 dB from 10 MHz to 100 MHz. It can be embedded in the bottom layer of a silicon substrate and sandwiched between system circuitries...
In this paper, a segmented IGBT gate driver IC for mitigating IGBT turn-on IC over-shoot is presented. The proposed IC is fabricated using TSMC's 0.18 μιη BCD Gen-2 process. Unlike existing IC over-shoot reduction techniques, the proposed technique does not require significant additional external components or an increase in turn-on energy. During turn-on, the gate driver is controlled such that (dV...
A new 1200V Pch-MOS having a new drain structure is proposed. Our proposing new 1200V Pch-MOS improves a substrate leak problem which occurred in conventional one without sacrificing a breakdown voltage and an output current. Thanks to the new Pch-MOS, a 1200V HVIC which provides a high voltage level-shifting from high voltage region to low voltage region is successfully realized.
A 30V power MOSFET technology, employing a low voltage superjunction approach, has been optimized for operation as a low-side switch in a DC-DC buck converter. In particular, this technology has been designed with an emphasis on minimizing the voltage overshoots that occur in high efficiency DC-DC converters by modification of the MOSFET's body diode and output capacitance, COSS. This has resulted...
We present an ultimately narrow pitch superjunction UMOSFET (SJ-UMOS) with a record low specific on-resistance (Rsp) for automotive applications. This high performance device was designed by not only shrinkage of lateral p/n pitch, but reduction of longitudinal dimension for voltage sustaining region including ion-implanted p-columns. The refined technologies brought us a fully depleted SJ structure...
A novel low voltage power MOSFET with a low threshold voltage (Vth) region (sub-MOS) is proposed. The proposed MOSFET has a superior trade-off relationship between output efficiency and switching noise, with a spike voltage 82% lower than a conventional MOSFET and the same efficiency at 300 kHz with an output current of 20 A. Since the proposed device reduces the drain current through rate (dir/dt)...
This paper presents recent advances and breakthroughs of an alternative 3D packaging solution for vertical power devices. Direct bonding technology and trench isolation used for power device islanding are the cornerstone of this scheme of integration. Involving direct copper bonding layers, the technology is used during the mid-process to enable the wafer level bonding of vertical power devices to...
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