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State-of-the-art closed-loop switched-capacitor (SC) designs usually regulate the output voltage by pulse frequency modulation (PFM) with the disadvantage of large electromagnetic interference (EMI). It may cause the failure of the Internet of Everything (IoE) devices. This paper proposes the hybrid digital low drop-out (DLDO) SC converter with a constant switching pulse width modulation (PWM) control...
A fully-synthesizable Physically Unclonable Function (PUF) with hysteresis-enhanced stability and active compensation of temperature variations is proposed. In detail, a bitcell based on low-voltage regulated Cascode current mirror is introduced. To reduce undesired bit flips, hysteretic behavior is obtained through the insertion of a Muller C-element output stage, which mitigates the effect of noise,...
An ultra low phase noise millimeter-wave (mm-wave) quadrature voltage-controlled oscillator (QVCO) is proposed. By introducing an additional coupling path and using uneven sized cross-coupled oscillators with a fully symmetrical layout, the phase noise and the amplitude/phase mismatches are minimized. Implemented in 90-nm CMOS process, the 67-GHz compact QVCO achieves 0.46 degree and 0.47 dB phase...
A quarter-rate 51Gb/s PAM4 CDR with decoded dual-NRZ outputs is presented for 400GbE optical transceivers. A baud-rate data-only sampling PD with zero-crossing integrating front-end is proposed to minimize the clock generation and distribution overhead, as well as improving the noise resilience under PAM4 low-SNR inputs. Measurement results show the CDR features 1.08ps RMS clock jitter, 3.4×10−9 PAM4...
In this paper, a single-inductor triple-input-triple-output (SITITO) buck-boost converter with cycle-by-cycle source tracking (CCST) is developed for multi-source energy harvesting. The proposed CCST is capable of harvesting power from the PV and TEG simultaneously, and automatically selects the appropriate source according to the maximum power point (MPP) of the transducers in each switching cycle...
This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running...
This work presents a fundamental-mode voltage-controlled oscillator (VCO) realized in a 130 nm SiGe BiCMOS process for operation up to 200 GHz. The implemented topology is derived from a feedback phase shifter design, which includes a wideband passive polyphase filter based on 90° and 180° transmission line couplers and a variable-gain active combiner. The fabricated circuit achieves a very large...
This paper describes an energy-efficient PAM-4 digital receiver based on sequence detection. This scheme takes advantage of the ISI in the channel to reconstruct the time domain 5-bit sequence including MSB and LSB. The architecture also enables built-in error correction with very low latency. This concept is demonstrated with prototype implemented in a 28nm FDSOI CMOS using only 18-data comparators...
This paper presents a novel three-dimensional maximum power point tracking (3D-MPPT) system for ultra-low power (ULP) solar energy harvesting systems (EHS) for internet of things (IoT) smart nodes. The proposed 3D-MPPT utilizes a gate-source voltage (Vgs) dependent switch width modulation (SWM) technique for improving power efficiency (PE) at standby (<1 μA) and heavy (>300μA) load scenarios,...
Two techniques for spur and phase noise cancellation have been proposed. A fully integrated design achieves a measured spur cancellation of 15dB at 250MHz and 750MHz offset as well as phase noise cancellation from 4MHz to 200MHz offset with maximum 25dB cancellation depth for a 1-GHz clock. The proposed ideas have been verified through a fabricated 65nm CMOS prototype with power consumption of 11mW...
A narrowband low-power low-sensitivity, IoT TxRx compliant to ARIB STD-T-67 & T-30, is presented. It employs (1) an injection locked IQ-divider without power-hungry high speed logic gates and flip flops to generate 25% duty cycle LO that drives the mixer following a simultaneously noise and impedance matched gm-boosted LNA, and (2) A dedicated pilot-less direct automatic frequency correction of...
In this paper, we propose a novel 24-transistor change-sensing flip-flop (CSFF) for ultra-low power applications. With the aid of an internal change-sensing unit, the proposed CSFF eliminates redundant transitions of internal clocked nodes when there is no change in the flip-flop content. No additional transistors are required compared to the conventional transmission-gate flip-flop (TGFF). Measurement...
In this paper, we present a Programmable SoC device with monolithically integrated RF-ADCs and RF-DACs in a 16nm FinFET process. The device includes quad ARM Cortex-53 and dual ARM Cortex-R5 processing subsystem, 750K programmable logic cells, 4000 DSP slices and 4 32Gb/s serial transceivers. Each 14-bit RF-DAC operates at a sample rate of up to 6.4GS/s and can directly synthesize RF carriers up to...
A Range Pre-selection Sampling (RPS) technique is introduced to reduce the input drive energy for SAR ADCs and is applied to a 10-bit 2MS/s SAR ADC in 65nm CMOS in this paper. Using the proposed RPS technique, the peak input sampling current and hence the input drive power requirement is reduced by a factor 2.4 as compared to conventional sampling (CS). Considering an ideal Class A operation for the...
A 0.5-V BJT-based thermal sensor design is first demonstrated in a 10-nm CMOS. A charge-pump technique is proposed for operating with a digital core supply voltage as low as 0.5 V without the restriction on forward junction bias (∼0.7V). A switched-capacitor integrator loop is presented for process-insensitive voltage-to-frequency conversion. This thermal sensor achieves an RMS resolution of ±0.173°C,...
Resistive RAM (ReRAM) is an attractive candidate for next generation embedded nonvolatile memory [1][2], with several advantages compared to conventional flash technology. First, ReRAM is a CMOS-compatible low temperature back-end of line (BEOL) memory. There is almost no mutual impact between ReRAM element and front-end CMOS devices during the wafer processing. Second, it only needs 2∼4 extra masks,...
This paper proposes the reconfigurable RX analog baseband transformer that supports multi-standard applications. The proposed ABB can transform its structure between a delta-sigma modulated ADC for narrow band and a baseband LPF for wide band with a simple switch configuration without extra cost. Thus, the ABB obtains efficiency in both size and power aspects. It occupies only 0.11mm2 of active area...
This paper presents an integrated wireless multiple sensors System-on-Chip (SoC) for healthcare including 3-lead ECG, bio-impedance (Bio-Z), and body temperature. To allow continuous and real-time monitoring, the SoC has included a multi-channel reconfigurable QPSK/BfSK transmitter (TX) to accommodate different power-constraint conditions. Fabricated in 130nm CMOS technology with a total die area...
A low-power and high-accuracy current driver IC is proposed for portable electrical impedance tomography (EIT) systems. The proposed IC supports active electrode configuration and has three key features. First, high output impedance current driver is implemented with phase compensation scheme through a delay-locked loop (DLL) to significantly alleviate a phase shift and a required power consumption...
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