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A 13-bit 160MS/s hybrid ADC in 65 nm CMOS is presented in this paper. By combining the pipelined, flash and SAR architectures, a hybrid ADC architecture is proposed to improve the power efficiency. An input offset storage technique of dynamic comparator is proposed to increase the conversion linearity. A reference voltage buffer with the charge compensation is proposed to save power and reduce the...
In this paper we present the first fully integrated analog LDO (low dropout regulator) for sub-0.5V supply voltages. The LDO can operate from 0.3V-to-1.0V input voltage, and can sustain a load variation of 10mA-to-100mA at 1.0V input and 5mA-to-25mA at 0.3V input. It achieves a peak 99.1% current efficiency for a 100mA load at 0.9V output voltage. In order to realize the gate drive at sub-0.5V supply...
This paper proposes a low-power, small formfactor all-digital RNG utilizing a concept of capacitive coupling between two ROs to amplify jitter and a dual-edge sampling scheme to increase the data rate. It is the most useful in battery-powered IoT applications where both energy and silicon area are critical constraints. The capacitive coupling effect with all digital circuit allows our design to operate...
An AES core designed for low-cost and energy-efficient IoT security applications is fabricated in a 65nm CMOS technology. A novel Dual-Rail Flush Logic (DRFL) with switching-independent power profile is used to yield intrinsic resistance against Differential Power Analysis (DPA) attacks with minimum area and energy consumption. Measurement results show that this 0.048mm2 core achieves energy consumption...
This paper presents a 1/4-rate PAM4 receiver employing a sampling decoder with an adaptive variable-gain rectifier (AVGR) to achieve a bit efficiency of 1.38 pJ/bit. By concurrently performing gain adaptation and amplitude rectification for decoding the least significant bit (LSB), the proposed decoder greatly reduces power consumption compared with the conventional full-rate topology using three...
This paper presents a 15-bit ΔΣ ADC with 10kHz-BW which can handle 30V CM voltages with high AC CMRR (in excess of 115dB at 10kHz) while operating from a 1.8 V supply. An HV capacitively-coupled chopper at its input enables the accurate sampling of input signals beyond the supply rails. Chopping is used to mitigate the ADC's offset and to enhance its CMRR, especially at high frequencies.
This work presents an area-efficient voltage and frequency scalable clock generator for low-power digital SoC clocking. Named Direct Digital Sampling and Synthesis (DDSS), the open-loop generator implemented in 28 nm FD-SOI operates from 0.45 V to 1.1V with measured jitter from 1.7% to 5.1% UI. Its low power consumption of 0.40pJ/cycle at 57 MHz 0.5 V combined with the ability to perform fast frequency...
This paper presents a compact audio delta-sigma modulator that features a scalable bandwidth to also support biomedical instrumentation such as digital hearing aids and electromyography, sustaining constant FoMS. The modulator achieves a small die area and low power consumption by exploiting the proposed dynamic gain-bandwidth-boosting (GBWB) scheme in the inverter-based class-AB OTA with minimal...
This paper describes a novel fully integrated 35GHz frequency modulated continuous wave (FMCW) PLL with twins-VCO to 7GHz sweeping bandwidth. The proposed FMCW PLL is composed of twins-VCOs, SDM modulator and waveform generator. A novel frequency sweeping extension (FSE) technique is proposed to make the twin-VCOs take turns to sweeping to realize wide sweeping bandwidth without sacrificing the sweeping...
This paper presents a 2-2 discrete-time sturdy multi-stage noise-shaping (SMASH) delta-sigma modulator using source-follower-based open-loop integrators. The resolution of the SMASH delta-sigma modulator is enhanced by eliminating the first-stage quantization noise from the output. Using the proposed source-follower-based open-loop integrator, the operating speed of the modulator is efficiently improved...
A 0.6-V, 200-kbps, 429-MHz ultra-low-power FSK transceiver (TRX) is presented. The receiver (RX) adopts a frequency-to-time based demodulator, which detects high or low frequency to determine data output level. The proposed RX achieves −85-dBm sensitivity at 0.1% BER and draws 0.146 mW. A 38.7% global efficiency, 429-MHz FSK transmitter (TX) is also reported in this paper. To remove the power-hungry...
This paper presents an energy-efficient symmetric block-wise concatenated-BCH (SBC-BCH) decoder architecture for energy-starving mobile storages. The proposed 4KB SBC-BCH code remarkably enhances the hard-decision-based error-correcting performance to defer the energy-consuming memorysensing operations for generating the soft-decision values, which are necessary to prolong the lifetime of flash memories...
This paper presents a 5-bit 2GS/s binary-search ADC. The proposed architecture prevents the use of a decoder to avoid the path delay racing between control signals and clock phases; thence the bit latency reduces to 1 single comparator delay only. We also propose a dynamic charge-steering comparator to quantize each bit quickly. Besides, we present well-balanced 1-of-N-to-Binary encoders to transform...
An energy-quality scalable (EQSCALE) feature extraction accelerator for IoT vision applications is presented. Knobs are introduced to dynamically adjust the tradeoff between energy and feature extraction quality, leveraging the intrinsic redundancy in video frames and the robustness of object recognition against missing features. Measurements of a testchip in 40nm show 310pJ/pixel energy at nominal...
To reduce conservative timing margin, many timing-error detection techniques by monitoring selected critical paths had been proposed. However, traditional adaptive methods incur significant area overheads and cannot prevent the error that is forming in the current clock cycle. In this paper, a low-overhead Transition-Detector (TD) with a 9-transistor current sensing circuit is proposed. TDs are inserted...
In this paper, we present a temperature compensated semi-digital integer-N PLL realized in a standard 130 nm CMOS technology, which achieves 48 fs rms phase jitter and a FOM of −245 dB. The presented design improves the phase noise performance of previously presented semi-digital PLLs by replacing the ring oscillator VCO by a semi-digitally tuned LC-tank VCO. In contrast to mostly digital PLLs, the...
A configurable neuro-inspired inference processor is designed as an array of neurons each operating in an independent clock domain. The processor implements a recurrent network using efficient sparse convolutions with zero-patch skipping for feedforward operations, and sparse spike-driven reconstruction for feedback operations. A globally asynchronous locally synchronous structure enables scalable...
In this paper, an amplifier-less digitally-controlled lithium-ion (Li-Ion) battery charger is presented. Owing to the digitally-controlled technique, the proposed charger eliminates all analog circuits and reduces the size of the power transistor. Hence, the proposed charger features a simple circuit structure and a small chip area. Additionally, this charger provides essential operations including...
This paper provides details on the new Broadwell server product family designed on 14nm Intel process. This was the first Xeon® server product on this process node. Low power, density optimized product, Broadwell-DE, has upto 8 dual-threaded 64b Broadwell cores [1], 12MB L3 cache, 2 10GT/s Ethernet KR lanes, 2 DDR4–2400MHz memory channels and 24 8GT/s PCIe lanes. Broadwell-SP, a high performance server...
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