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3D QLC (Quad-Level-Cell) NAND technology with 16 voltage levels per cell will be one of the next generation memory technologies after 3D TLC (Triple Level Cell) NAND flash succeeded. Besides, program algorithm for 16 voltage levels is studied in this paper, the important read algorithms are investigated because the data errors of QLC device will be easily generated due to power loss, program distribute,...
We report on the gate misalignment induced asymmetry to enhance the impact ionization in Germanium (Ge) Junctionless (JL) devices by localizing the carrier depletion to a narrow region of the semiconductor film. Results show that misaligned Ge JL MOSFET can exhibit higher values of impact ionization power per unit volume which leads to a sharp current transition with nearly an ideal Subthreshold swing...
In this paper, we study the effects of two important parameters such as work function of gate material and the temperature, on behavior of FinFET device. The investigation is carried out on Germanium based FinFET device. Working device shows improve current drivability in terms of high on current (ION), less leakage current (IOFF), high value of (ION/IOFF), and have good control on short channel effects...
Toom-Cook algorithm is a well-known method to compute large integer multiplication. In this paper, we propose an implementation of 272 bit multiplier based on Toom-Cook algorithm and finish the hardware implementation. Sythesizing with Synopsys Design Compiler in the SMIC 65nm CMOS process, the result shows that the design based on Toom-Cook can acheive at least 22.9% less on area and 43.4% less on...
Organometal halide perovskite material was investigated as a promising candidate for resistive random-access memory (RRAM). In order to improve the stability of perovskite RRAM, a polymethyl methacrylate (PMMA) interlayer was inserted between perovskite and metal electrode. High ON-OFF current ratio (106) and operating voltage as low as 0.5 V were achieved in the PMMA encapsulated perovskite RRAM.
This paper presents a Soft-Edge Error-Detecting Flip-Flop (SEED FF), which can be used in Ultra-Low-Voltage (ULV) digital circuits to address timing variation problems with a lower timing error correction rate. The master latch's clock edge of a timing error detecting flip-flop is delayed so that it has not only the timing error detection capability but also a narrow transparency window. HSPICE simulations...
A compact narrow-band low temperature co-fired ceramic (LTCC) filter with a fractional bandwidth of 3% is proposed. The proposed filter consists of five cascaded half-wavelength resonators vertically arrayed on each LTCC layer. End-coupling between adjacent resonators is precisely controlled by rectangle-shaped slot on intermediate ground layer. The overall size of the filter is only 8 × 6 × 0.89...
This paper presents a 10-bit 100-MS/s 2b/cycle-assisted SAR ADC in a 180nm CMOS technology. The proposed 2b/cycle-assisted architecture can effectively speed up ADC operation and improve the ADC linearity. To maintain a small capacitor mismatch, dual-reference C-DACs are proposed to avoid using a tiny unit capacitance. At 100-MS/s, it consumes 6.45 mW from a 1.8-V supply. Measured Nyquist SNDR and...
In this paper, the impact of gate voltage on the electron injection in a recently reported tunneling contact IGZO TFT has been studied. The dependence of the injection current on the temperature indicates thermionic emission dominates at small gate bias, while tunneling begins to contribute at large gate bias. The Schottky-barrier height at the metal/graphene/IGZO interface has been extracted, which...
A programmable gain amplifier (PGA) with DC offset cancellation (DCOC) is designed by 0.18 μm CMOS process in this paper. The PGA adopts two-stage in cascade based on a novel feedback structure, which realizes a constant 3-dB gain step and avoids using multiplexing decoder. The proposed DCOC function block features an adequately low cut-off frequency and completes the challenge of integration on chip...
A new CMOS readout circuit with non-uniformity calibration for diode uncooled infrared focal plane array (IRFPA) is presented in this paper. A new transconductance amplifier with offset cancellation structure is proposed, utilizing output offset voltage storage. The bias current of each pixel is adjusted by a current splitting DAC array, calibrating the mismatch of the current sources and the non-uniformity...
A novel SOI trench LDMOS with vertical double-RESURF is studied in this paper. A p-type silicon pillar is inserted beside the oxide trench as a vertical double RESURF layer, which can effectively modulate the electronic field and enhance the doping concentration in the drift region. The drain n+ region extends to the surface of buried oxide layer, shortening the motion-path in the high-resistance...
A super-pixel based on-chip compression is proposed in this paper. The compression is achieved by reading only one sample for each super-pixel. The proposed technique and the corresponding circuit are simulated in MATLAB and UMC 180 nm CMOS technology, respectively. Higher values of PSNR are observed as compared to the state-of-the-art on-chip compression techniques. For the compression factor of...
We present a TCAD process and analytical model based simulation analysis to investigate the effect of different stressors on nanowire FETs. We have utilized stress profiles extracted from TCAD process simulations and calculated mobility enhancement using the second-order piezoresistive model. Our analysis includes strained CESL and strained gate fill material for a gate-last process. Our process simulations...
This work presents a self-adaptation algorithm to automatically adjust the peaking settings of a continuous-time linear equalizer (CTLE) in a high-speed PAM4 receiver. A statistical approach is adopted to improve the robustness and flexibility of the adaptation algorithm. The PAM4 top level distribution around the peak value of several consecutive top levels guides the CTLE to attain the optimal digital...
In this paper, low cost 1200V UHV LDMOS device has been proposed. As BVD and Ron are contradictory, so to make low Ron, high breakdown voltage is the challenge of this paper. The key feature of this device is the linear P-top which is used to obtain best charge balance, and increase the diffusion current to move faster in the drift region which reduces the electric field and substantially helps to...
This paper mainly presents a design of optimized (15, 4) parallel counter. When testing the design with 15 rows of inputs, synthesis report of our design performs better in respect of delay, area and power consumption than other two existing design. This result shows that processes such as partial product reduction in a multiplier or column-addition in a matrix could be more efficient, especially...
For the first time, this paper reveals and explains the detailed contribution of the main-junction lateral resistive zone to the ruggedness of high-voltage fast recovery diodes during a harsh reverse recovery. And its optimized width is discussed.
We present an energy efficient QRS detector for real-time ECG signal processing implemented in ASIC. An adaptive thresholding scheme based on forward search interval (FSI) algorithm together with simple preprocessing is proposed to accurately detect QRS peaks. The Verilog HDL codes with improved hardware utilization efficiency are validated using FPGA, achieving 99.59% sensitivity (Se) and 99.63%...
The bipolar resistive switching properties of the CBRAM device are investigated for nonvolatile memory applications in a SiO2/ZrO2/SiO2 structure. The device shows good switching characteristics with set/reset voltages less than + 1 V/−1 V with a variation of less than 0.2 V. The SiO2/ZrO2/SiO2 tri-layer CBRAM device exhibits excellent memory performances, such as stable DC endurance up to 103 cycles...
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