The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
As the progress of the process technology, the clock mesh design has been widely used in high-performance circuit to reduce the clock skew. Since the uniform mesh design cannot avoid hot spots, the non-uniform mesh design is more useful for avoiding the timing variation caused by high temperatures. In this paper, we propose an integer linear programming (ILP) approach to reduce the wire length of...
Data compression technology is the necessary technology in the age of big data. Compared with software compression techniques, hardware compression techniques can improve speed and reduce power consumption. LZMA is a lossless compression technology, and its hardware implementation has broad application prospects. This paper proposes a novel high-performance implementation of the LZMA compression algorithm...
In this work, an automatic gain control amplifier for high voltage spindle recording is proposed. It is composed of a fix-gain amplifier and a variable gain amplifier (VGA) with threshold detecting logic to control the gain of VGA. The system provides 3 different gain set: 54dB, 60dB and 66dB. The bandwidth of the system covers from 0.5Hz to 1.5 KHz. The power is 7.7uW, and the integral input referred...
A 10–60 Gb/s wireline transmitter with a 4-tap multiple-multiplexer (MUX) based feed-forward equalization (FFE) is presented. It adopted a novel 4:1 MUX to increase the bandwidth of the final seiralizing stage. Simulation result shows that the proposed 4:1 MUX operates over a wide range of data rate between 10 and 60 Gb/s. Designed in 65 nm CMOS technology, the transmitter exhibits a low jitter of...
Real-time lossless compression can reduce the burden of big data transmission and storage. Hardware compression is faster and more energy saving when compared with software. This paper proposes a novel LZO hardware architecture and various acceleration methods, integrates the compressor module and other IP modules. Finally, test and demonstration are provided on the DE2 development board. The results...
Karatsuba Multiplication Algorithm is commonly used in modular multiplications of public-key cryptosystems with large key sizes. The overlapped summation in Karatsuba Multiplication is difficult for parallel acceleration in hardware implementations. This paper proposes a method of avoiding the overlapped summation under the circumstances of calculating Montgomery Modular Multiplication. The proposed...
This paper presents the FPGA implementation of neuron block units based on a sigmoid activation function for artificial neural networks (ANNs) applications. The Coordinate Rotation Digital Computer (CORDIC) algorithm has been employed for the approximation of sigmoid activation function. The proposed design was simulated using ModelSim XE II and synthesized using Altera's Quartus II with a Cyclone...
In this paper, a low-cost accelerator for the ηT pairing in characteristic three over the super-singular elliptic curves is designed. As the critical operations of ηT pairing, the cubing and sparse multiplications over GF(36m) in the Miller's algorithm are merged and their arithmetic are modified and scheduled to reduce the intermediate data related overhead. With these optimizations, the Miller's...
A new technique to reduce the clock jitter effect on single-bit continuous-time delta-sigma modulators (CTDSM) is proposed. It utilizes a delay line to generate N highly correlated clock sources to reconstruct the feedback waveform. Theoretical analysis show that the jitter-induced random noise power is reduced by a factor of 1/N2. Simulation results confirming the analysis are reported.
This paper shows the circuit level performance comparison of low-κ and high-κ spacer Junctionless FinFET(J-FinFET). TCAD simulations show that for high-κ (HfO2, κ=22) spacer J-FinFET, the device performance parameters such as DIBL (drain induced barrier lowering), SS (sub-threshold swing) and ION/IOFF improved by 14.5 %, 5% and 3.5x respectively as compared to low-κ (SiO2, κ=3.9) spacer J-FinFET....
A low power magnetic field sensor fabricated with sectorial split-drain MAGFET (SSD-MAGFET) in conventional 2.5μm metal gate CMOS process with a digital readout circuit that outputs pulse width modulated (PWM) signal linearly related to the magnetic field strength acting on the device is presented. Resistive trimming circuits are applied to achieve offset and sensitivity adjustment. Using 5V supply...
In this paper, we review the key performance of optical modulators operating in the wavelength range of 1.3–1.5 μm for fiber-optic link applications and compare the design of two nanoscale modulators which are based upon (a) second-harmonic generation (SHG) from GaN nanopillars and (b) electrooptic polymer in nanoslot waveguides, respectively.
In this paper, a new design of Terahertz (THz) Ring Hybrid Coupler Based on Parallel Plate Dielectric Waveguide with Signal Line inserted (PPDWS) is proposed. The PPDWS is a simple transmission line, easy to fabricate, with a low average loss of 0.45dB/mm at 1–1.4THz, and designed to be implemented into the THz Ring Hybrid Coupler Design. We employ (3N+1.5)λ for the circumference of the Ring Hybrid...
A design of switched-inductor solar energy harvesting circuits for wireless microsensors is proposed. To track the maximum power point (MPP) for the photovoltaic (PV) array, a Boost harvester is designed. A Buck converter working in the discontinuous conduction mode (DCM) is utilized to provide the stable output voltage and improve efficiency.
A modified structure of operational transconductance amplifier (OTA) in CMOS 65-nm technology with signal-current enhancer and slew-rate (SR) helper is presented in this paper. The bias current is chosen to be lower than 0.1 μA to reduce the overdrive voltage requirement and thus make the amplifier survive under 0.7 V supply. An SR helper is also introduced to improve the transient performance. As...
This paper proposes the use of FIR+SC DAC in sigma delta modulator is an approach to balance insensitivity to clock jitter noise and power efficiency. An example is implemented in UMC 180nm technology and simulation results show that it achieves SNDR 77.2dB and 83 μW power consumption in 100kHz bandwidth, which corresponds to FoMw 71fJ/conv.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.