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The most of the memristor based applications which have been proposed so far have not considered the parasitic components. In this paper, we apply a generic memristor model which includes the parasitic effects to our proposed memristive logic architectures. First, we show that the current response of the memristor has the decaying oscillation when the unit step function is applied. Then we demonstrated...
The demands of high-speed and power-efficient systems have resulted into the emergence of the approximate computing. Existing approximate circuits as well as stochastic techniques have shown promising advances in improving various figures of merit. However, a through fair comparison of arithmetic units still remains an issue which has not been studied. This paper reviews the prerequisites for a fair...
Internet services tend to include more and more multimedia traffic. Exchange of high resolution video and voice streams is now many users' common need. To cope with the increasing requirements of video transmissions in sufficient time and optimal bandwidth without quality loss, effective compression algorithms are required. The Quadtree Structured Differential Pulse Code Modulation (QSDPCM) technique...
Lately, the advancement in circuit technology combined with the design of low cost embedded devices have resulted in an infiltration of the latter into everyday humans' lives. To exploit the full potential of ubiquitous embedded devices, a network is used for their inter-communication, offering advanced real-time monitoring. This paradigm, known as Internet of Things (IoT), is steadily consolidated...
Cellular Automata (CAs) is a well-known parallel, bio-inspired, computational model. It is based on the capability of simpler, locally interacting units, i.e. the CAs cells, to evolve in time, giving rise to emergent computation, suitable to model physical system behavior, prediction of natural phenomena and multi-dimensional problem solutions. Moreover, at the same time CAs constitute a promising...
In this paper, we propose Without Charge Sharing Quasi Adiabatic Logic (WCS-QuAL) as a countermeasure against Power Analysis Attacks. We evaluate and compare our logic with the recently proposed secure adiabatic logic designs SPGAL and EE-SPFAL at frequencies ranging from 1MHz to 100MHz. Simulation results show that WCS-QuAL outperforms the existing secure adiabatic logic designs on the basis of %...
We present a silicon nanowire-based field-effect transistor biosensor with Schottky barriers for highly specific and sensitive human α-thrombin detection. The active sensor area is decorated with thrombin-binding aptamers as receptor molecules. Each sensor chip is integrated into a microfluidic device for flow-through measurements. Instantaneous detection is provided by real-time monitoring of FET...
This paper presents the energy analysis of capacitive adiabatic logic (CAL) based on gap-closing MEMS devices. CAL uses variable capacitance components instead of transistor elements to have a new balance between on- and off-state losses. Ultra-low power consumption in CAL requires an energy efficient way for charging and discharging of the variable capacitance. First, we investigate “pure” electrical...
This paper proposes a topology optimization method for dual-threshold (DT) independent-gate (IG) FinFET circuits. In the proposed method, a node extraction algorithm is developed to extract the characteristic nodes of a BDD expression, which are suitable to be realized with the compact logic gates based on the DT IG FinFET devices, and then the equivalent replacement program that these extracted characteristic...
This paper presents the design, simulation implementation and evaluation of a novel 3D NoC router that combines buffered and bufferless routing. Our proposal is an asymmetrical router that is buffered in the z dimension and bufferless in the x- and y dimensions. Experimental results show that the proposed router effectively combines the advantages of both buffered and bufferless routers. Compared...
The simulation of aging induced degradation mechanisms is a challenging task during the design of digital systems. Parametrical degradations can be handled most accurately at TCAD level, as the physical models like [1] and [2] can be implemented directly. On the other hand, timing failures caused by such degradations cannot be assessed exactly lower than Register Transfer Level (RTL), where the notion...
In this paper, a methodology for substrate noise reduction in mixed-signal integrated circuits (IC) in lightly doped substrates is proposed. The methodology is based on separating a digital aggressor circuitry into two power domains, one closer and one more distant from the victim. By proper assignment of digital modules in one of those two domains, substrate noise sensed by an analog victim is reduced...
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