The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
To enhance the mask rejection below 2 MHz for effective human body communication (HBC), a new mask shaping technique is proposed for the HBC transmitter, where a digital sigma-delta modulated infinite impulse response (IIR) filter provides sufficient rejection with a digital-to-analog converter (DAC) of only 8 bits. A receiver with high input impedance is designed to improve the sensitivity, and a...
A 900 MHz RF energy harvesting system is proposed for a far-field wireless power transfer application. The topology of a single-stage CMOS rectifier loaded with an integrated boost DC-DC converter is implemented in a 40 nm CMOS technology. The co-design of a cross-coupled CMOS rectifier and an impedance matching network is described to optimize RF-DC conversion efficiency for the target input power...
A low-voltage, ultra-low power sensor interface for electromyogram (EMG) signal acquisition is presented. The sensor interface consists of an amplifier and a SAR ADC that work from a 0.3V supply. The low-voltage amplifier topology provides a noise level of 26μVrms, 40dB gain and a state-of the art power efficiency factor (PEF) of 2.2 from a 20–425Hz bandwidth. Low-voltage supply improves the power...
This paper presents a multi-channel transmitter (TX) architecture that uses only a single bulk acoustic wave (BAW) resonator while covering 88 MHz of bandwidth. The proposed architecture overcomes the limited tuning range of a single BAW resonator by combining the BAW tuning range with a programmable integer-N frequency division and RF single-sideband (SSB) mixing approach. The single-BAW multi-channel...
This paper presents a 60 GHz class-E digital power amplifier (DPA) that generates energy-efficient, non-constant envelope modulations up to 25 Gb/s. The DPA achieves a peak drain efficiency of 17.7% at a Vsat of 7.4 dBm. By means of direct digital amplitude modulation of the 6-bit output stage, the DPA produces error-free, high-order constellations (16-QAM, 32-QAM, 64-QAM) up to 5 GSym/s with error...
An 8-way phased array TRX front-end with RF phase shifting and on-chip TR switching is implemented in 28nm CMOS . The TX OP1dB and RX NF are 10dBm and 6.8dB, respectively. The active phase shifter shows less than 5° phase resolution and amplitude errors within ±0.35dB. The 9.6mm2 chip consumes 231mW in RX and 508mW in TX mode from a 0.9 V supply. When combined with PCB antennas, a ±46° scan angle...
This paper presents a 15-bit digital power amplifier (DPA) with 1.6W saturated output power. The topology of the polar switched-current DPA is discussed together with the architecture of the output transformer which is implemented in BEOL as well as in WLCSP metal layers. The chip is fabricated in a standard 28nm CMOS process and exhibits an EVM of 3.6%, E-UTRA ACLR of 34.1dB, output noise of −145...
A system for mmW LO signal generation targeting 5G is presented. The proposed concept achieves high LO spectral purity at mmW frequencies using standard CMOS SOI technology. The measured performance is in line with 5G outdoor system requirements, which due to multi-path propagation require a smaller sub-carrier spacing than recent indoor mmW systems like IEEE 802.11ad. A set of two fractional-N, PLL...
A 28nm CMOS 1.2GHz full-duplex analog front end (AFE) is presented. The AFE can deliver 20Gbps of aggregate service across 50m of RG6 coax. The on-chip line driver, powered from a 7.2V supply and using core transistors, delivers 5.9Vptp differential to the line through the hybrid. A tunable capacitive hybrid circuit for full duplex operation is proposed for low noise performance and allows channel...
A 25MS/s 70.1dB-SNDR 5.3mW 0.11mm2 pipelined ADC has been achieved by the low-cost 0.18μm CMOS. The proposed simple MDAC is implemented by only capacitors, switches, power supply voltage and source-follower buffer without requiring the dedicated voltage reference to attain the passive residue amplification. The prototype has achieved by far the smallest chip size and the excellent Schreier FOM of...
Piezo-electric harvesting systems have proved to be a promising alternative to batteries for supplying portable devices. Recent trends focus on the reduction of the size of piezo-electric transducers through the development of nanostructured materials which exhibit output power levels in the order of few microwatts as well as maximum open voltage sources lower than 2 V. In this paper, we propose a...
This paper presents CMOS monolithic PPG sensor with distributed 1b delta-sigma light-to-digital convertor (LDC). Proposed unbiased photodiode (PD) based circuit with fully integrated PD in the same die efficiently performs direct light to digital conversion, and the distributed architecture further improves the dynamic range. The implemented sensor, fabricated in standard 0.18μm CMOS process, achieves...
The paper demonstrates improved power side channel attack (PSCA) resistance of a 128-bit AES engine in 130nm CMOS using random fast voltage dithering (RFVD) enabled by integrated inductive voltage regulator (IVR) and all-digital clock modulation (ADCM). The measured power signatures at AES and IVR supply nodes show 9× reduction in peak test vector leakage assessment (TVLA) metric while also protecting...
A 402–405 MHz MICS-band wake-up receiver is presented that achieves −63.8 dBm sensitivity at 4.5 nW. High sensitivity at 400 MHz is accomplished via an 18.5 dB passive voltage gain transformer filter loaded by a high input impedance (Rin > 30 kΩ), high scaling factor (kED > 300), 1.8 nW current re-use pseudo-balun envelope detector, while low power is achieved by operating all active circuits,...
This paper presents a constant with temperature (CWT) voltage reference generator (VRG) that utilizes only regular transistors in standard CMOS technology. By operating an NMOS transistor as a self-biased current source driving a diode-connected PMOS transistor in the subthreshold region, a sub-pW, temperature stabilized voltage can be generated. To improve line regulation, a self-regulation NMOS...
In this presentation we review the evolution of radio access networks and introduce 5G, based on the current plans and expectations, as reported in the recent series of the Ericsson Mobility Reports. Standardization is an on-going effort, and much industry research is devoted to finding a good match of requirements — balancing system performance, flexibility and implementation imphcations. We present...
A low-noise readout interface integrated with an antenna-coupled FET-based terahertz (THz) detector is designed and fabricated in a 0.15-μm CMOS standard technology. The implemented readout includes a cascade of a preamplification noise reduction stage based on a parametric chopper amplifier, and a direct analog-to-digital conversion by means of an incremental ΣΔ converter, substituting the lock-in...
The thermal diffusivity of silicon DSi has been used to realize fully-CMOS frequency references. However, due to the temperature dependence of Dg, the accuracy of such frequency references is limited to about 1000 ppm (−55 °C to 125 °C, one-point trim) due to the inaccuracy of the on-chip temperature compensation circuitry. As an alternative, we propose a frequency reference based on the thermal diffusivity...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.