The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The demand for more and more efficient management of power systems is causing BCD technologies to move forward in the integration of additional digital functions, and the use of microcontrollers in products has become a common practice. In this perspective, the introduction of an embedded nonvolatile memory (eNVM) to store the microcontroller code has become important to enable software customization...
This paper describes a fully integrated 65nm CMOS 2×2 MIMO multi-band LTE RF transceiver for small cell (femtocell) base stations with frequency support from 680MHz to 6GHz. The transceiver features highly integrated RF front-ends including single-ended LNAs and drive amplifiers with total 32 individual RF I/O pins. The receiver shows NF of 2.9∼5.2dB, HP3 of >-2dBm, and HP2 of >48dBm over the...
A low-power radio analog front-end which includes a self-interference (SI) cancellation circuit and a harmonic-rejection power amplifier (HRPA), is proposed to reduce the interaction between a transmitter (TX) and receiver (RX), to enable full-duplex operation. A prototype TSMC device demonstrates more than 30dB SI cancellation over a 4MHz BW and a PA 3rd and 5th harmonic reduction of 30dB and 15dB,...
An I/Q RF-DAC featuring two 6-bit DAC elements driven in quadrature, each with its own on-die antenna, and a total EIRP of 13.2 dBm, is demonstrated in a 45-nm SOI-CMOS technology. The 129–143-GHz carrier signal is first amplified by the 30-dB gain LO path and is directly modulated by the 12 baseband bit streams, without linear upconversion or power amplification. QPSK, 8-PSK, 16-QAM, 32-QAM, and...
A 1.25GS/s 7b single-channel SAR ADC is presented with an SNDR/SFDR of 41.4dB/51dB at low frequencies, while the SNDR/SFDR at Nyquist are 40.1dB/52dB and remain still 36.4dB/50.1dB at 5GHz. The high input frequency linearity is enabled by a fast bootstrap circuit for the input switch, while the high sampling rate, the highest among recently published >34dB SNDR single-channel SAR ADCs is achieved...
This work presents a System-on-Chip designed for Energy-Harvested applications. It embeds an ARM® Cortex®-M0+ microcontroller, 4KB RAM, 4KB ROM, an ultra-low power frequency synthesizer, a custom power switch, and a Power Management Unit enabling Active and Sleep modes. The system fabricated in 28 nm FD-SOI technology achieves 2.7pJ/cycle at 16 MHz during active mode, and the core consumes 4.3 nW...
A 12 b 600 MS/s 2 × TI SAR ADC achieving 60 dB SNDR at Nyquist is presented. Time-interleaving errors are calibrated in the background by using a linear but noisy reference ADC. A test chip demonstrates that interleaving spurs are reduced to below −70 dBFS using an off-chip least-mean-squares (LMS) algorithm. The reference ADC is an 8 b SAR with reduced sampling capacitance and input amplitude. This...
A DDR4 transmitter (TX) for direct-attach memory on a processor chip is presented as well as the design of the associated low-dropout linear voltage regulators (LDO) that generate the split-mode supply voltages for the thin-oxide protection of the TX output stages operated from the 1.2 V DDR4-supply. The TX uses AC-boost equalization. Signal-integrity (SI) simulations have shown that pre-emphasis...
A SiGe BiCMOS Colpitts VCO with a transformer-coupled varactor operating from 18.8 to 23.1 GHz is presented. The Colpitts topology is leveraged to trade a slight degradation in the oscillator figure-of-merit for very low phase noise. The oscillator features a state-of-the-art phase noise of −119.4 dBc/Hz at 1 MHz offset from the carrier, while drawing 17.5 mA from the 4 V supply. The oscillator FoM...
This work presents the first transimpedance amplifier with a common gate input stage and a voltage-controlled resistor fabricated using organic thin-film transistors on a flexible plastic substrate. The presented circuit is tested in a photodetector application and shows a very low power consumption of 1.6 μW. The voltage-controlled resistor is the first resistor based on organic thin-film transistors...
A sun sensor implemented with a spiking pixel matrix is reported. It is the very first one based on an asynchronous event-based pixel array. A paradigm associated to classic digital sun sensors is solved with this approach. Only pixels illuminated by the sun light are readout. Hence, the output data flow is quite reduced. The computational load to resolve the sun position is quite low, comparing to...
This paper presents a relaxation oscillator that utilizes a supply-stabilized pico-powered voltage and current reference (VCRG) to charge and reset a chopped pair of MIM capacitors at sub-nW power levels. Specifically, a temperature- and line-stabilized reference voltage is generated via a 4-transistor (4T) self-regulated structure, the output of which is used to bias a temperature-compensated gate-leakage...
This paper presents a mmW frequency generation stage aimed at minimizing phase noise via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A second-harmonic tank resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for shortest and well controlled common-mode current return path. Class-F operation...
A dynamic bias pre-amplifier based latch type comparator is designed in a 65nm CMOS process. Its performance is compared with the double-tail latch-type comparator fabricated on the same chip in terms of energy consumption, input referred noise and speed. Measurements demonstrate that the proposed dynamic bias pre-amplifier based comparator consumes 2.8 times less energy per comparator operation with...
In this work, an improved topology of a relaxation oscillator is proposed, dealing with the non-idealities of the comparator stage. The oscillator test chips, manufactured in 0.35-μm CMOS process, have the nominal frequency of 1 MHz and typical power consumption of 210 μW. The area of the oscillator core is 0.04 mm2. The measured temperature variation of the output frequency is ±0.4% in the temperature...
This paper describes an op-amp with a novel Class-AB Push-Pull output stage employing a “constant-transconductance” cell for keeping the amplifier gain-bandwidth product constant over different load conditions. A biasing scheme is also examined to define the quiescent current of the op-amp. The circuit is part of the current sensing scheme for a DC-DC Buck converter. The proposed system has been built...
A 120GHz in-band full-duplex PMF transceiver with tunable electrical-balance duplexer with on-chip antenna is implemented in a 40nm bulk CMOS tech-nology. The self-interference (SI) cancellation is performed with a fully-differential transformer-based electrical-balance duplexer, resulting in a SI suppression of 30dB over a bandwidth of more than 14GHz. The insertion loss of the duplexer is less than...
In this paper, we present a pseudo-resistor-based transimpedance amplifier (TIA) whose transimpedance value is PVT-independent and continuously tuneable over a wide range. The nonlinearity of the pseudo-resistors is mitigated by connecting a large number of elements in series and the effect of process variations on the pseudo-resistor is canceled by a biasing network based on a pseudo current mirror...
A solid state 3D scanner based on a pulsed laser diode source and narrow time gating of a 2D CMOS single photon avalanche diode (SPAD) detector array is presented. The imager uses an on-chip delay-locked loop to program the time gating of 40 sub-arrays individually. The prototype detector has 80 × 25 pixels with a fill factor of 32 % in the sensor area. The chip has been fabricated in a 0.35 μm high-voltage...
A wideband auxiliary receiver embeds a band-reject N-path filter in the low-noise amplifier to improve the compression point. The receiver has high input impedance and it can be placed at the transmitter output without loading effects. Implemented in a 28nm CMOS technology it occupies 0.12mm2 active area and it can withstand up to +4 dBm QPSK modulated 20 MHz signal with less than 1-dB noise degradation...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.