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Neurophysiological architecture using 3D integration technology offers a high device interconnection density as well as fast and energy efficient links among the neuron and synapses layers. In this paper, we propose to reconfigure the Through-Silicon-Vias (TSVs) to serve as the neuronal membrane capacitors that map the membrane electrical activities in a hybrid 3D neuromorphic system. We also investigate...
The growing demands of large capacity flash-based storages have facilitated the down-scaling process of NAND flash memory. Among NAND flash technologies, 3D charge trap flash is regarded as one of the most promising candidates. Owing to the cylindrical geometry of vertical channels, the access performance of each page in one block is distinctive, and this situation is exaggerated in the 3D charge...
Internet-of-Things devices need sensors with low power footprint and capable of producing semantically rich data. Promising candidates are spiking sensors that use asynchronous Address-Event Representation (AER) carrying information within inter-spike times. To minimize the overhead of coupling AER sensors with off-the-shelf microcontrollers, we propose an FPGA-based methodology that i) tags the AER...
Vectorless integrity verification is becoming increasingly critical to robust design of nanoscale power delivery networks (PDNs). To dramatically improve efficiency and capability of vectorless integrity verifications, this paper introduces a scalable multilevel integrity verification framework by leveraging a hierarchy of almost linear-sized spectral power grid sparsifiers that can well retain effective...
Hold time fixing ensures correct data synchronization, which is essential and serves as the final step of timing closure for IC design. Conventionally, buffer insertion is adopted to fix hold time violations; buffers, however, induce routing difficulty, increase area utilization, and contribute leakage power. Therefore, in this paper, we propose to fix hold time violations by free metal segment allocation...
Flow-based microfluidic biochips have attracted much attention in the EDA community due to their miniaturized size and execution efficiency. Previous research, however, still follows the traditional computing model with a dedicated storage unit, which actually becomes a bottleneck of the performance of biochips. In this paper, we propose the first architectural synthesis framework considering distributed...
In this paper, a novel Greybox design methodology is proposed to establish a design and co-optimization flow across the boundary of conventional software and hardware design. The dynamic timing of each software instruction is simulated and associated with processor hardware design, which provides the basis of ultra-dynamic clock management. The proposed scheme effectively implements the instruction-based...
Deep Neural Networks (DNNs) have emerged as a powerful and versatile set of techniques showing successes on challenging artificial intelligence (AI) problems. Applications in domains such as image/video processing, autonomous cars, natural language processing, speech synthesis and recognition, genomics and many others have embraced deep learning as the foundation. DNNs achieve superior accuracy for...
Modern DRAM suffers from a new problem called row hammering. The problem is expected to become more severe in future DRAMs mostly due to increased inter-row coupling at advanced technology. In order to address this problem, we present a probabilistically managed table (called PRoHIT) implemented on the DRAM chip. The table keeps track of victim row candidates in a probabilistic way and, in case of...
Logic locking is a technique that has been proposed to thwart IC counterfeiting and overproduction by untrusted foundry. Recently, the security of logic locking is threatened by a new attack called SAT attack, which can effectively decipher the correct key of most logic locking techniques. In this paper, we propose a new technique called delay locking to enhance the security of existing logic locking...
Quantum computers1 could revolutionize computing in a profound way due to the massive speedup they promise. A quantum computer comprises a cryogenic quantum processor and a classical electronic controller. When scaling up the cryogenic quantum processor to at least a few thousands, and possibly millions, of qubits required for any practical quantum algorithm, cryogenic CMOS (cryo-CMOS) electronics...
Various side-channel attacks (SCAs) on ICs have been successfully demonstrated and also mitigated to some degree. In the context of 3D ICs, however, prior art has mainly focused on efficient implementations of classical SCA countermeasures. That is, SCAs tailored for up-and-coming 3D ICs have been overlooked so far. In this paper, we conduct such a novel study and focus on one of the most accessible...
This paper shows that performing an XOR operation between the outputs of parallel arbiter PUFs generates a more secure output at the expense of reduced stability. In this work, we evaluate the security and stability of XOR PUFs using 1,000,000 randomly chosen challenges, applied to 10 custom-designed PUF chips, tested for 100,000 cycles per challenge, under different voltage and temperature conditions...
Many applications, such as machine learning and data sensing are statistical in nature and can tolerate some level of inaccuracy in their computation. Approximate computation is a viable method to save energy and increase performance by trading energy for accuracy. There are a number of proposed approximate solutions, however, they are limited to a small range of applications because they cannot control...
Aggressive pitch scaling in sub-10nm nodes has introduced complex design rules which make routing extremely challenging. Cell architectures have also been changed to meet the design rules. For example, metal layers below M1 are used to gain additional routing resources. New cell architectures wherein inter-row M1 routing is allowed force consideration of vertical alignment of cells. In this work,...
AUTOSAR (AUTomotive Open System ARchitecture) provides an open and standardized E/E architecture for automobiles. AUTOSAR systems exhibit real-time requirements, i.e., an AUTOSAR application must always be schedulable. In this paper, we propose an overhead-aware method to find schedulable design configurations for an AUTOSAR application. We show how to construct a timing model for the application,...
Incremental timing-driven placement (TDP) is one of the most crucial steps for timing closure in a physical design. The need for high-performance incremental TDP continues to grow, but prior studies have focused on optimizing only setup timing slacks, which can be easily stuck in local optima. In this paper, we present a useful skew methodology based on a maximum mean weight cycle (MMWC) approach...
Upcoming high-bandwidth protocols like Ethernet TSN feature mechanisms for redundant and deterministic (scheduled) message delivery to integrate safety- and real-time-critical applications and, thus, realize mixed-criticality systems. In existing design approaches, the message routing and system scheduling are generated in two entirely separated design steps, ignoring and/or not exploiting the distinct...
This paper presents a novel secure hardware description language (HDL) that uses an information flow type system to ensure that hardware is secure at design time. The novelty of this HDL lies in its ability to securely share hardware modules and storage elements across multiple security levels. Unlike previous secure HDLs, the new HDL enables secure sharing at a fine granularity and without implicitly...
Fault attacks recover secret keys by exploiting faults injected during the execution of a block cipher. However, not all faults are exploitable and every exploitable fault is associated with an offline complexity to determine the key. The ideal fault attack would recover maximum key bits with minimum offine effort. Finding the ideal fault attack for a block cipher is a laborious manual task, which...
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