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We examine highly-stable black phosphorus field-effect transistors and demonstrate that they can exhibit reproducible characteristics for over ten months. Nevertheless, we show that the performance of these devices is affected by thermally activated charge trapping in oxide traps. In order to characterize these important traps, we introduce a universal experimental technique which allows for an accurate...
Key challenges in providing ESD protection for High Voltage CMOS technology is presented in this paper. Based on that, various methodologies to make the high voltage power transistor ESD self-protecting without changing the device IV characteristics and dimension, for different HV technologies is outlined.
Electrodeposited cobalt has received significant attention in recent years as a suitable metallization alternative for many interconnect technologies. For instance, Co is being evaluated as back-end-of-line (BEOL) alternative for Cu in 10 nm node technologies due to challenges with scaling the diffusion barrier at small CDs and increasing electron scatter in small features [1]. A super-conformal Co...
CVD and more recently ALD have become methods of choice for the deposition of new materials, to deal with the 3D nature of new devices, and to meet the requirement for atomic level thickness control. Several examples illustrate how precursor design can contribute to keeping the cost of new materials deposition in control, whether through easier facilitization thanks to better physical properties,...
Energy performance of nonvolatile power-gating (NVPG) that is a power-gating technique with nonvolatile state/data retention is demonstrated for nonvolatile SRAM (NV-SRAM) with spintronics retention and silicon-on-thin-BOX (SOTB) CMOS technologies. The NV-SRAM cell consists of an ordinary 6T cell and two magnetic tunnel junctions (for nonvolatile retention) with two pass-transistors. The cell and...
Atomic layer deposition (ALD) is widely in use for depositing a variety of materials, such as metal oxides, metal nitrides and metals, in a conformal and defect-free form at low temperatures on high aspect-ratio substrates. These advantages make ALD uniquely powerful method for applications where sensitive substrate materials combine with extreme demands on coating quality and temperature/chemical...
The SOI floating body effect and to keep floating on both the N layer and the body are important for appearance of the super steep SS on the PN-Body tied SOI FET. It was confirmed for the first time with measuring the new test devices.
Transition from planar MOSFETs to FinFETs enabled scaling beyond 28nm node. At 5nm/3nm design rules, a transition from FinFETs to nanowires has to be evaluated. We explore with rigorous NEGF (Non-Equilibrium Green's Functions) and sub-band Boltzmann transport models the impact of nanowire shape and SiGe/Si cladding layers on its performance and variability. Outside of the nanowire channel, a “bottleneck”...
Interstitial trapping by oxygen-inserted silicon channel results in blocking of boron and phosphorus transient enhanced diffusion as well as retention of channel boron profiles during the gate oxidation process. The enhanced doping profile control capability is applicable to punch-through stop of advanced CMOS devices and its benefits to 28nm planar CMOS and 20nm bulk FinFET devices projected by TCAD...
Integrated Circuit (IC) was invented in 1958 in the process of challenges to “Tyranny of Numbers”. We face the same challenge again with the end of Moore's Law and rise of IoT. A near-field coupling integration technology (Fig.1) is proposed as a new solution in very large system to replace mechanical connections by electrical ones. This paper presents two technologies. ThruChip Interface (TCI) replaces...
A comprehensive and rigorous computational study at atomic level was performed for various vertical tunneling field-effect transistor (VTFET) structures based on III-V and two-dimensional (2D) materials. The key challenges of VTFETs were found to be induced by device structures and the channel materials' properties. An optimized VTFET structure was proposed to suppress the parasitic tunneling current...
We describe the effect of microwave heating on C3H5 carbon cluster ion implanted epitaxial wafers using a high dose amount of carbon cluster ion implantation condition. A high dose amount condition of C3H5 carbon cluster ion implantation generates implantation-related defects, such as stacking faults, after epitaxial growth. Therefore, we investigated the control and reduction of stacking faults using...
We describe IBM's roadmap for Neuromorphic Technologies to drive next-generation cognitive computing, ranging from nanodevice-based hardware for accelerating well-known supervised-learning algorithms (which happen to rely on static, labeled data), to emerging, biologically-inspired algorithms capable of learning from temporal, unlabeled data. The various hardware-centric neuromorphic projects currently...
Two new processes for deep junction formation have been demonstrated with low thermal budget UV excimer laser annealing using the melting regime: (i) in-depth controllable activation after high energy implantation and (ii) diffusion and recrystallization after heavily-doped Si deposition.
In this paper, the impact of fin number on device performance and hot carrier induced device degradation was investigated for n-channel tri-gate multi-fin FinFET with different fin numbers. The threshold voltage (VTH) shift, transconductance, and subthreshold swing degradation were extracted to determine the degradation of device. It was found that the device with fewer fins shows better device performance,...
This paper presents a card-type acoustic emission wave (AE) sensor with symmetrically four-beam structures and thermal actuators providing normal enhanced forces to increase signal-to-noise ratio (SNR). The enhanced force applied to the sensing beam can be observable by thermal imager. The location of AE source can be detected by this developed single sensor, greatly improving the conventional method...
In this work, we proposal a ferroelectric domain to enhance program/erase/read efficiency of conventional charge-trapping nonvolatile memory. The ferroelectric-domain-dominated HfZrO/HfON memory shows the better subthreshold characteristics than control charge-trapping structure (HfO2/HfON). Additionally, the memory speed with ferroelectric polarization (∼800ns) is more than three orders of magnitude...
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