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The randomness and unpredictability of Random Telegraph Noise (RTN) of 16nm FinFET Dielectric (FIND) RRAM is firstly implemented to Time-Contingent Physical Unclonable Function (PUF) application. A novel 3D Time-Contingent Physical Unclonable Function (TC-PUF) realized by 1Kbit 16nm FinFET Dielectric (FIND) RRAM has been newly proposed and demonstrated on a pure 16nm FinFET CMOS logic technology....
In this work, we fabricated the Pt/NbOx/Pt MIT device showing threshold switching. XPS results revealed that there are mixed NbO2 and Nb2O5 phases in the NbOx thin film. The self-oscillation of NbOx device with a resistor has been demonstrated, showing its feasibility as an oscillation neuron.
Low temperature wafer scale direct bonding technology using plasma activated bonding (PAB) for heterogeneous photonic device integration is reviewed. Nitrogen plasma irradiation in a high vacuum chamber allows tight strength bonding between InP-based and SOI wafers with the bonding temperature of 150°C as well as low damage to GaInAsP quantum wells (QWs). In contrast Argon irradiation cause poor bonding...
Device performance enhancement elements are frequently reducing device reliability margin in scaled CMOS technologies. To assess the impact of HCI degradation on digital CMOS logic we study the frequency degradation (Δf/f) of ring oscillator circuits using core and IO devices in 14nm FinFET technology and correlate the results with discrete device degradation using the conventional DC and a novel...
Random telegraph noise (RTN) is one of major recent transistor reliability concerns in designing reliable systems. In a circuit that contains a large number of small transistors, the impact of RTN-induced fluctuation is considered to increase when it is compared with the static frequency variation caused by manufacturing process. The impact of RTN on process variation is described based on our measurement...
For the first time, analytical equations for skin and proximity effects are derived to successfully describe current distributions in advanced CMOS technology interconnects subject to high-frequency signals. The analytical solution matches simulations evaluating skin depth as a function of interconnect geometry and operating frequency.
We investigated the endurance characteristics of a Cu-doped HfO2 selector device in one transistor-one selector (1T1S) structure, which is fully compatible with standard BEOL process. The device exhibits high endurance of 1010 under 10 μΑ compliance current. However, reduced endurance (105) was observed as increasing the compliance up to 100 μΑ. Under the condition of high operation, intrinsic defect...
High performance InGaZnO TFT with high-k Al2O3 gate dielectric were fabricated and its photoresponse to ultraviolet illumination was compared to a control TFT with SiO2 dielectric. Due to the incorporation of Al2O3, its saturation mobility is increased for 7.4 times, and its photoresponsivity (∼400A/W) is boosted for 103 times along with a significantly improvement in linearity and contrast ratio...
The aim of our investigation is to develop complete electro-mechanical system simulation. The present developed prototype system includes pressure sensors, amplifiers, a controller, servo motors, and a robot-body. Sensor signals such as transduced voltage, servo motor actuation signals such as shaft angle, velocity, and acceleration are modeled in an analytical way. The entire system structure is...
3D printing is used to fabricate molds for micro-structuring the polydimethylsiloxane (PDMS) film. The fabricated sensor device using the micro-structured PDMS film presents high sensitivity, excellent durability and fast response, and is also shown to perform reliable real-time wrist pulse monitoring.
This work demonstrates high quality Ge/GeO2 interfaces fabricated by O2 RTA that are degraded by a good quality SiO2 layer deposited by ALD. However, neither O3 and H2O precursors commonly used during subsequent high-k ALDs nor Si precursor AP-LTO-330 do not degrade the interface. Thus Dit increase after SiO2 deposition is likely due to intermixing. Therefore, the effect of subsequent ALDs on the...
This study proposes an innovative method to measure the variation of cell leakage current. Extreme cell leakage determines DRAM refresh time (tREF). Although the average leakage current from the test element group (TEG) has been the only index for determining cell leakage, it does not provide the distribution of unit cell leakage. We find that cell leakage distribution can be calculated from the slope...
Physics-based TCAD simulations of measured vertical and lateral InAs/Si hetero nanowire tunnel FETs are presented to demonstrate the effect of major non-idealities on slope and ON-current. The Dit limit for sub-thermal TFET operation is predicted, and it is shown that a high defect density at the InAs/Si interface can result in a slope close to 60 mV/dec due to thermionic emission in an arising MOSFET...
The latest development results for flexible and printed electronics technology based on organic thin-film transistor (OTFT) devices as well as printable semiconductors and metal nanoparticles are briefly reported in this paper. The successful fabrication and operation of printed OTFT devices and potential integrated circuit applications such as flip-flop logic gates and operational amplifiers will...
We presented a self-organized, MOS gate-stacking structure of SiO2/Ge-dot/SiO2/Si1−xGex-shell, using thermal oxidation of poly-Si0.85Ge0.15 nanopillars over buffer Si3N4 on the Si substrate, for the fabrication of high performance Ge-dot photo MOSFETs. Low dark current of 3 μA/μm2, Superior high photo responsivity of 1400–710A/W, and short response time of <0.8ns are measured on 90nm Ge-dot photo...
To improve the crystallinity of multilayer graphene (MLG) directly deposited on SiO2 for interconnect applications, a new solid phase precipitation (SPP) process involving current stress is investigated. It is found that the MLG crystallinity precipitated from a Cu capped Co-C layer can be improved by the vertical current to the Cu/Co-C but not by the horizontal current. The current enhanced SPP (CE-SPP)...
Specifications and fabrication process suitable for a small wafer with the diameter of half-inch, which is used for a minimal fab, is presented. We beveled wafer edge by rapping and polishing in order to clean the edge and to suppress the strong surface tension at the edge. To show the crystallographic orientation of the wafer, we introduced laser marking process. By the processes, we have formed...
The growth mechanism of GeOx layer formed by plasma post oxidation at room temperature (RT PPO) is investigated based on angle resolved X-ray photoelectron spectroscopy (AR-XPS). The experimental results show that the GeOx grown by RT PPO does not obey layer-by-layer growth mode. And the distribution of Ge oxidation states is random during RT PPO. These findings are helpful to the optimization of...
The contact property between Ge2Sb2Te5 (GST) with vertical carbon nanotubes (CNTs) is studied in this work. By careful catalyst design and process optimization, we have demonstrated the formation of ohmic contact between the CNT and the GST material. The developed process is CMOS compatible and can be used for form phase change memory over the vias in the interconnect layers.
In this paper, we report the anomalous behavior of capacitances in halo channel MOSFET for the linear and saturation regions. Unlike MOSFETs these devices have different threshold voltage (VTH) for the DC and CV operations, and therefore cannot be modeled by conventional methods. We have investigated various cases of doping non-uniformity: Source side halo (SH), Drain side halo (DH), both side halos...
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