The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Energy and power consumption are major limitations to continued scaling of computing systems. Inexactness where the quality of the solution can be traded for energy savings has been proposed as a counterintuitive approach to overcoming those limitation. However, in the past, inexactness has been necessitated the need for highly customized or specialized hardware. In order to move away from customization,...
This talk presents some of the prominent barriers to designing energy-efficient circuits in the sub-14nm CMOS technology regime and outlines new paradigm shifts necessary in next-generation multi-core microprocessors and systems-on-chip. Emerging trends and key challenges in sub-14nm design are outlined, including (i) device and on-chip interconnect technology projections, (ii) performance, leakage...
With the growing popularity of mobile devices, the trend in the field of system-on-chip has shifted from high performance to low power operation. However, traditional design methodology is limited by the design margins reserved for process, voltage and temperature variations. Therefore, a systematic solution that enables real-time timing error detection and correction was proposed to eliminate redundant...
We present a new scheme of buffer implementation in through-silicon via (TSV) based 3D circuits at early layout design stage for total delay minimization. For optimal buffer insertion at floorplanning level, it is important to incorporate more accurate and realistic estimation of interconnect delay and power. Early prediction of delay and power leads to better design decisions, overall timing closure...
Many-Core System-on-Chips (MCSoCs) require efficient task migration approach in order to reach system performance objectives such as load balancing, communication optimization, fault tolerance, and temperature control. In this paper an efficient self-aware migration approach is introduced for NoC-based MCSoCs using a centralized feedback controller in order to control the congestion over the system...
Efficient handling of faults during operation is highly dependent on the interval (latency) from the time embedded instruments detect errors to the time when the fault manager localizes the errors. Detection and localization latencies are dependent on the network connecting fault-monitoring instruments to the fault manager. The network can be dedicated to fault-monitoring data, or used for functional...
Physical unclonable functions (PUFs), are a new type of physical security primitive which enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). Due to their flexibility and lower time to market, FPGAs are increasingly used for many applications. Arbiter PUFs (APUFs) are among the most widely studied...
This paper presents a multiplication reduction technique through near-zero approximation, enabling embedded learning in resource-constrained IoT devices. The intrinsic resilience of neural network and the sparsity of data are identified and utilized. Based on the analysis of leading zero counting and adjustable threshold, intentional approximation is applied to reduce near-zero multiplications. By...
Modern SOCs may be composed of hundreds of individual physical modules, referred to as tiles. The total number of scan channels servicing these tiles often greatly exceeds the number of SOC device pins available to connect those channels to test equipment. Traditional reliance on a small number of pin-to-channel test mode configurations, predetermined in hardware, results in inefficient scan data...
It is our pleasure to warmly welcome you to the 29th IEEE International System-on-Chip Conference. The 2016 edition of the SoC conference is hosted in the beautiful city of Seattle, WA (USA). The Seattle area is a hot-bed of technology research and development with companies such as Amazon, Boeing, and Microsoft as well as universities like the University of Washington calling it home. With such a...
Very-long-instruction-word (VLIW) architectures are widely adopted in high-performance and low-power digital signal processors (DSP) due to their simplicity from extensive software optimizations. However, their poor code density (usually > 2× code size for a given application) and corresponding instruction accesses can overwhelm the energy savings on DSP datapaths. This paper presents variable-length...
The self-dual graph is a beautiful topic in graph theory. Based on DeMorgan's theorem, all CMOS circuits are series-parallel graphs. Thus self-dual graphs are few in CMOS circuits. The paper reveals a self-dual diamond-graph CMOS H-bridge circuit family, and then displays the characteristics and properties of the self-dual graphs on CMOS circuits. A basic diamond graph makes an H-bridge on the circuit...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.