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We show the first camera based (privacy-preserving) indoor mobile positioning system, CaPSuLe, which does not involve any communication (or data transfer) with any other device or the cloud. The algorithm only needs 78.9MB of memory and can localize a mobile device with 92.11% accuracy. Furthermore this is done in 1.92 seconds of on-device computation consuming 3.77 Joules of energy, as evaluated...
In this paper, a hardware ASIC implementation of the Numenta Hierarchical Temporal Memory (HTM) algorithm is presented. Each column in the neural network is implemented as a processing element (PE). Neuron cells in columns are built as identical cell modules. Dedicated register files for each module cell are employed to replace the conventional centralized memory organization. A complete neural network...
Sample preparation is one of the most crucial processes in most biochemical applications. Reagents are repeatedly diluted in an appropriate sequence to get a target solution with a specific concentration value. For flow-based microfluidic biochips (FMFBs), several research works have been proposed for reactant minimization. In this paper, we propose the first sample preparation algorithm for microfluidic...
Sample Adaptive Offset (SAO) is a new tool added in latest video coding standard (HEVC) to achieve better coding efficiency resulting in higher visual quality. In this paper, we propose efficient and high performance VLSI architecture as well as data transfer scheme for SAO decoder that can work in a pipelined manner achieving 4K (Ultra-HD) resolution at 60 fps in video codec engine. The proposed...
For almost 30 years, the IEEE International System-on-Chip Conference (SOCC) has been the premier forum for sharing advances in system-on-chip (SoC) technologies, designs, tools, test and verification. The SOC conference rotates amongst international locations, and attracts researchers and engineers from all over the world to exchange knowledge, share experiences and establish collaborations with...
With degradation in transistors dimensions and complication of circuits, Three-Dimensional Network-on-Chip (3-D NoC) is presented as a promising solution in electronic industry. By increasing the number of system components on a chip, the probability of failure will increase. Therefore, proposing fault tolerance mechanisms is an important target in emerging technologies. In this paper, two efficient...
The Internet of Things is creeping into ever more critical areas of our lives. From drug pumps to aircraft, connected cars and even smart weapons - there are few products coming off the production line today which don't have an added element of ‘intelligence’ and connectivity. There's just one problem: they are fundamentally flawed. And in this brave new world, that could result not just in data theft...
This paper discusses the performance impact of interconnect parasitic resistance and capacitance for SoC (System on Chip) design beyond 10-nm FinFET technology. As technology scaling advances, the impact of BEOL (Back End of Line) is recognized as one influencer on operating performance. Using typical logic standard cells, sensitivity analysis by DOE (Design of Experiments) shows that the parasitic...
Quantum-well infrared photodetectors (QWIPs) have become research focus in recent years due to its many inherent properties. However, the measurement of internal parameters is very difficult; instead, computer simulation and device modeling provide a better way to analyze quantum structure devices. In order to solve this issue, the electronics performance and the optical performance of a QWIP fabricated...
This paper presents a low power ΣΔ CMOS modulator with op-amps operating in subthreshold region for processing bio-signals. In order to reduce a power consumption of the proposed fourth order ΣΔ CMOS modulator, two opamps for implementation of integrators are designed to be operating in subthreshold region. For furthermore power reduction, the first two integrators are re-utilized with switches and...
In the design flow of multi-processing system-on-chips (MPSoCs), the evaluation of communications structures, particularly, networks on chip (NoCs), plays a very important role, since it may show relevant characteristics on performance, energy consumption or cost. Simulation under a number of stimulus given by a traffic generator is a relevant solution for MPSoCs performance analysis. Traditional...
In-situ timing error detection and correction mechanisms (such as Razor) monitor the performance of actual datapaths, and are believed more resilient in adaptive voltage scaling (AVS) systems, especially when considering local variations. However, Razor has serious hold time problems, of which the overwhelming buffer padding makes it infeasible in advanced process technologies. Pre-error (or in-situ...
The emergence of Internet-of-Things has imposed more stringent security requirements on SoC devices. Basic security requirements include confidentiality and integrity, which imply less observability and controllability of the SoC from the outside world. On the other hand, observability and controllability are essential to SoC debug activities. Without bearing in mind the conflicting nature of security...
This paper presents a technique that utilizes comparator timing information to accelerate successive approximation register (SAR) analog-to-digital converter (ADC) conversion process. With the scaling down of power supply voltage, the comparator delay is exponentially increasing. Thus, more information can be potentially extracted from the comparator transient response. In the proposed approach, the...
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