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Embedded DRAM (eDRAM) is becoming more and more popular as a low-cost alternative to on-chip SRAM. eDRAM is particularly attractive for frame buffers in video applications with ever increasing screen resolutions. However, eDRAM suffers short retention time and high refresh power, which prevents its widespread adoption. To save the refresh power of eDRAM-based frame buffers, we propose Tiered-Reliability...
Power and energy are key design considerations across a spectrum of computing solutions, from large-scale data centers and supercomputers to mobile phones and wearable computers. Correspondingly, all these systems need to focus on efficiency: achieving higher performance and functionality at improved resource and energy usage. At the same time, emerging workload and technology trends provide additional...
In this paper, we minimize 3D clock power using shutdown gates to selectively turn off unnecessary clock activities. In 3D-IC, shutdown signals require large-sized Through-Silicon-Vias(TSVs), so we propose a simulated annealing(SA) based algorithm along with a force-directed TSV placer to decide the selection of shutdown gates and the locations of TSVs under layout whitespace constraint. Furthermore,...
Non-volatile memories are gaining significant attention for embedded cache application due to their low standby power and excellent retention. Domain wall memory (DWM) is one possible candidate due to its ability to store multiple bits per cell in order to break the density barrier. Additionally, it provides low standby power, fast access time, good endurance and retention. However, it suffers from...
This paper outlines leakage mitigation in smart phone SoCs. Leakage power will be investigated across the disparate smart phone use-cases. Leakage mitigation techniques will be covered at architecture, design, and run-time.
Decoders for Low Density Parity Check (LDPC) codes, used commonly in communication networks, possess inherent tolerance to random internal computation errors. Consequently, it is possible to apply voltage over-scaling (VOS) in their implementation to save energy. In this paper, the impact of VOS on timing errors is characterized for a typical min-sum LDPC decoder architecture using circuit simulations...
Software-based path delay fault testing (SPDFT) has been used to identify faulty chips that cannot meet timing constraints due to gross delay defects. In this paper, we propose using SPDFT for a new purpose - aggressively selecting the operating point of a variation-affected design. In order to use SPDFT for this purpose, test routines must provide high coverage of potentially-critical paths and must...
In this paper, emerging low-power interconnect options for CMOS and beyond CMOS technologies are reviewed. First, electrical interconnects based on carbon nanotubes and graphene nanoribbons are discussed. It is found that carbon-based electrical interconnects can potentially outperform their conventional Cu counterpart at technology nodes close to or below 10 nm. Next, since using electron spin as...
Energy consumption of memories is always a significant issue for computing systems. Recently, hybrid PRAM and DRAM memory architectures have been proposed. It combines the advantages of DRAM and PRAM, such as low leakage power in PRAM and short write latency in DRAM. However, the leakage power in DRAM is still considerable in hybrid memories. The leakage power can only be reduced by turning DRAM into...
Resonant clocking has emerged as a promising approach for achieving energy-efficiency in high-performance digital systems. However, the limited frequency range of efficient resonant clocking operation restricts its applicability in widely-used Dynamic Voltage and Frequency Scaling (DVFS) systems. Existing frequency-scalable resonant clocking implementations are either not voltage-scalable, or provide...
The variability of deep-submicron technologies creates systems with asymmetric cores from a frequency and leakage power viewpoint, which makes an opportunity for performance-power optimization. In particular, process variation can transform a homogeneous many-core platform into a heterogeneous system where the task mapping becomes extremely difficult. In this paper, we propose a mapping algorithm...
A memory rename table for improved performance, reduced complexity, and reduced energy consumption is proposed and evaluated. It gives an average 8.7% speedup and 7.9% reduction in core and cache energy. The evaluation employs a simulation model for an out-of-order core, similar to the ARM Cortex A15, and McPAT for energy measurements. The improvements are the result of filtering nearly half (45.4%)...
For set-associative caches, accessing cache ways in parallel results in significant energy waste, as only one way contains the desired data. In this paper, we propose Tag Check Elision (TCE): a non-speculative approach for accessing set-associative caches without a tag check to save energy. TCE can eliminate up to 86% of the tag checks (67% on average), without sacrificing any performance. These direct...
Improving the endurance of Phase change memory (PCM) is a fundamental issue when the technology is considered as an alternative to main memory usage. Existing wear-leveling techniques overcome this challenge through constantly remapping hot virtual pages, engendering a fair amount of extra write operations to PCM and imposing considerable energy overhead. Our observation is that it is unnecessary...
This paper demonstrates that a partially solar powered EV can significantly save battery energy during cruising using innovative fast photovoltaic array (PV) reconfiguration. Use of all the vehicle surface areas, such as the hood, rooftop, door panels, quarter panels, etc., makes it possible to install more PV modules, but it also results in severe performance degradation due to inherent partial shading...
As technology scaling is coming to an end, 3D integration is a promising technology to continue transistor density scaling in the future and facilitate new architectural designs. However heat removal is a serious challenge in 3D ICs. A promising solution is micro-fluidic (MF) cooling. In this paper we argue that aggressive cooling methods are necessary to unlock the true potential of 3D ICs. We simulate...
This paper presents a converter for boosting the low-voltage output of thermoelectric energy harvesters to power standard CMOS circuits. The converter can start up from a fully de-energized state off a bipolar ±40 mV input and can harvest net positive energy from voltages as low as ±30 mV in steady state. A single transformer is multiplexed between an oscillator that is used during startup and a flyback...
This paper presents a large advance in energy-efficient operating system multiprocessor task scheduling with experimentally proven benefits for standard Linux multi-core computing platforms. This Energy Aware Scheduler (EAS) introduces micro-Operations executed Per Joule (OPJ) as a metric representing run-time task energy efficiency. A novel platform architecture permits event-resolved real-time energy...
This paper analyzes the effect of variations in the parameters of an Integrated Voltage Regulator (IVR) and its impact on the power/performance of a system of IVR driven digital logic circuit. The coupled analysis of IVR and digital logic considering variations in the integrated passives, power train FETs and controller transistors shows, compared to an off-chip VR, variations in IVR induce much larger...
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