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Advanced 0.16 μm BCD technology platform offering dense logic transistors (1.8 V-5 V CMOS) and high performance analog features has been developed. Thanks to dedicated field plate optimization, body and drain engineering, state of the art power devices (8 V to 42 V rated) have been obtained ensuring large Safe Operating Areas with best RONXAREA-BVDSS tradeoff.
In this paper we describe the development of integrated lateral thyristors in NXP's proprietary HV-SOI technology [1]. Thyristors are typically used for their extreme high-current capability or their zero-crossing switch-off, that allow easy implementation of phase-controlled power conversion. In this work, the main motivation to select thyristors is their ability to operate as an efficient switch...
We report our development of a novel NLDMOS in SOI based smart power technology, integrated into Freescale's 0.13μm CMOS platform. The new NLDMOS not only achieves BVDSS up to 140V in both low side and high side operations, but more importantly, the Rdson∗Area is able to shrink at least 35–40% below the current benchmark, which is the lowest reported for BVDSS ranging from 50V to 138V. For the first...
This paper discusses the priority issues on the energy infrastructure before and after the Great East Japan Earthquake in Japan. For the issue before the earthquake “Development and implementation of technologies that realizes a co-existence between sustainability and living comfortableness,” seven technologies are explained, such as “Improvement of efficiency in Energy use” including “Improvement...
Heavily doped GaN nanochannel FinFET has been proposed and fabricated, for the first time, which does not have any p-n junction or heterojunction. In spite of its easy and simple epitaxial growth and fabrication process, the fabricated device with nanochannel width of 80 nm and gate length of 1 μm exhibited excellent off-state performances such as extremely low off-state leakage current of ∼ 10−11...
Integrated in a 0.35 μm 700 V BCD process platform, ultra-low Ron, sp 700 V self-ISO (isolated) and NISO (non-isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) are proposed in this paper. 800 V and 780 V are achieved for NISO and ISO DB-nLDMOS, of which Ron, sp are 11.5 Ω·mm2 and 11.2 Ω·mm2, respectively. Utra-low Ron, sp benefits from optimized device size and strict limitations for annealing temperature...
A new 1200V Pch-MOS having a new drain structure is proposed. Our proposing new 1200V Pch-MOS improves a substrate leak problem which occurred in conventional one without sacrificing a breakdown voltage and an output current. Thanks to the new Pch-MOS, a 1200V HVIC which provides a high voltage level-shifting from high voltage region to low voltage region is successfully realized.
This paper presents recent advances and breakthroughs of an alternative 3D packaging solution for vertical power devices. Direct bonding technology and trench isolation used for power device islanding are the cornerstone of this scheme of integration. Involving direct copper bonding layers, the technology is used during the mid-process to enable the wafer level bonding of vertical power devices to...
A new concept to realize the usage of a high-voltage bootstrap diode without substrate leakage current for 120V high-side-driver application is proposed and verified by 2D simulation. The combination of high-voltage (HV) JFET and medium-voltage (MV) diode with proper modification to avoid substrate leakage current at forward conduction state and high-blocking voltage at off state for integrated bootstrap...
New 60V-class intelligent power switch (IPS) technology implementing a vertical trench MOSFET has been developed for automotive applications. We have realized the method to integrate a 60V-class vertical trench MOSFET with high voltage surge robustness and 5V- and 60V-class lateral planar MOSFETs on one chip. The integrated vertical trench MOSFET is designed by 0.35μm-rule in order to reduce its specific...
Vertical diodes with breakdown voltages up to 2.6kV have been fabricated on bulk GaN substrates. The measured figures-of-merit of these devices show performance near the theoretical limit of GaN. These vertical GaN diodes exhibit robust avalanche breakdown behavior with a positive temperature coefficient. System-level performance advantages have been demonstrated in power conversion applications....
In this work, we developed a HB1340-0.13um BCD technology of the complimentary LDMOS including fully isolated structure device with dual drift layer. We could achieve LDMOS with best-in-class trade-off between specific on-resistance and breakdown voltage by its optimized drain engineering. The HB1340 process in 0.13um 1.5V/5V/6V CMOS technology platform can provide various kinds of high voltage devices...
In this paper, we discuss the fundamental design tradeoff among specific on-resistance (Ron, sp), gate charge (Cgg), quasi-saturation, and reliability characteristics for an integrated high voltage LDMOS. A novel patterned gate design is proposed and implemented in a 120V-rated NLDMOS. Optimal design characteristics are demonstrated with 30% improvement in switching FOM (Ron, sp∗Qgg) and a robust...
A high speed lateral SOI IGBT (BM-LIGBT) with an electronic barrier modulation structure, which was not reported in previous literatures, is proposed in this paper in order to remarkably improve turn-off speed of the SOI LIGBT. Two important mechanisms are realized in this device: one is the electronic barrier modulation for speeding up the device turn off and for providing the same injection efficiency...
An ultra-low specific on-resistance (Ron, sp) high voltage trench SOI LDMOS based on the enhanced bulk field (ENBULF) concept is proposed. The key feature of this new device is heavily doped N/P pillars parallel to the trench oxide layer. The bulk electric field of the trench LDMOS is enhanced both in the dielectric and the silicon layer by using the N/P pillars. Firstly, the highly doped N/P pillars...
In this paper, we present high threshold voltage, low on-resistance, and high speed GaN-HEMT devices using a p-GaN layer in the gate stack. There are three novel features — first, for the first time, p-GaN gate HEMTs were fabricated on a 200-mm GaN on Si substrate using a Au-free fully CMOS-compatible process. Second, good electrical characteristics, including a threshold voltage of higher than 2...
Normally-off AlGaN/GaN MOS HEMTs were successfully fabricated and investigated by simple KOH wet etch and rf-sputtered HfO2 as a gate insulator. The proposed KOH wet etch resulted in an adequate recess-depth and smooth etched surface. The gate-recessed HEMT exhibits threshold voltage (Vth) shifts from −3 to 1.5 V after 150 s KOH-wet etch. The breakdown voltage of 1580 V and Ron, sp of 8.09 mΩ·cm2...
Open-base breakdown voltages as high as 10.5 kV (91% of theoretical avalanche limit and 125 V/μm), on-resistance of 110 mΩ-cm2 close to the unipolar limit of 94 mΩ-cm2, and current gain as high as 75 are measured on 10 kV-class SiC BJTs. Monolithic Darlington-connected BJTs fabricated on the same wafer yield current gains as high as 3400, and show Si BJT-like output characteristics with a differential...
We proposed a PNM-IGBT [1] that can realize performance close to the theoretical limit shown by Nakagawa, et, al [2, 3]. In that work, we confirmed PNM-IGBT can achieve a very low saturation voltage due to its great injection enhancement effect. However, it is accompanied by a slight increase in turn-off-loss. We believe that we can diminish this increase by our unique control technique. Therefore,...
In this paper, we report our recently developed 2nd Generation, large-area (56 mm2 with an active conducting area of 40 mm2) 4H-SiC DMOSFET, which can reliably block 1600 V with very low leakage current under a gate-bias (VG) of 0 V at temperatures up to 200°C. The device also exhibits a low on-resistance (RON) of 12.4 mΩ at 150 A and VG of 20 V. DC and dynamic switching characteristics of the SiC...
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