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The 20-way set associative 2.5MB slice ported L3 cache for the multi-core Xeon® Processor uses 0.108 um2 cell in a 22nm tri-gate technology with 2.7TB maximum bandwidth. It is protected by double-error correction/triple-error detection ECC. The basic building block is designed to support floorplan style on each processor with large L3 cache. On die fuse storage enables high resolution repair coverage...
This work presents a novel 77GHz automotive radar providing detection distance and angle up to 100m and ±8°, respectively. Using a 1TX/4RX array, this radar system employs various mmWave techniques to fulfill the expected SNR.
Fast boosting of supply rails is critical for near-threshold computing to overcome serial code bottlenecks. A novel supply boosting technique, called Shortstop, boosts a 3nF core in 26ns while maintaining acceptable supply voltage droops. The innate parasitic inductance of a dedicated dirty supply rail is used as a boost-converter and combined with an on-chip boost capacitor. Shortstop boosts a core...
A serial I/O receiver efficiently implements a decision feedback equalizer (DFE) employing 2 IIR taps for improved long-tail ISI cancellation. The use of a modified multi-input two-stage slicer allows for both DFE summation to be performed directly at the slicer and optimization of the first-tap IIR filter/mux feedback path to allow for cancellation of the critical first post-cursor. Fabricated in...
A motion estimation (ME) processor for H.264 encoder is implemented in 40nm CMOS. With algorithm and architecture co-optimization, its throughput reaches 1.59Gpixel/s for 7680×4320p 48fps video, at least 7.5 times faster than previous chips. Its core power dissipation is 622mW at 210MHz, with energy efficiency improved by 23%. DRAM bandwidth requirement is reduced by 68%. With a maximum search range...
We propose a maximum power point tracking (MPPT) circuit for micro-scale sensor systems that measures ripple voltages in a switched capacitor energy harvester. Compared to conventional current mirror type MPPT circuits, this design incurs no voltage drop and does not require high bandwidth amplifiers. Using correlated double sampling, high accuracy is achieved with a power overhead of 5%, even at...
A 5Gbp/s mobile memory I/O interface at sub-1.0V supply voltage with Low Voltage-Swing Terminated Logic (LVSTL) using a VSSQ (Ground) termination and an adaptive reference voltage calibration scheme is presented. Power efficiency is 2.4mW/Gbps/pin in 20nm mobile DRAM process, which is 44% lower value than that of LPDDR3.
A 6.0-W bi-directional DC-DC converter has been developed for a wireless power transceiver which enables a mobile device to receive and transmit power wirelessly. When transmitting power, a mobile device can function as a wireless power station for another mobile device. Implemented in a 0.35-µm BCDMOS process, the DC-DC converter shows 91-% peak efficiency and the wireless power transceiver employing...
This paper presents a wireless transceiver for WSNs using insects. It employs current reuse, switch-less switching, and fast PLL on/off switching techniques to reduce the power, size, cost, and weight of the sensor node. Implemented in 130-nm CMOS technology, the transceiver merges VCO, PA, LNA, TX/RX switch, and modulator into a common branch to reduce its power and complexity. In TX mode, the transmit-power...
An adaptive PLL implemented in a 0.9V 32nm process achieves optimal clock data compensation across a wide range of PVT and operating conditions. This is accomplished by an automated supply-noise sensitivity tracking loop which constantly monitors the BER of a tunable critical path circuit. The proposed PLL achieves a 14.5% to 15.6% improvement in processor Fmax over a conventional design for a 90mV...
This paper presents a wide-band analog Fractional-N clock synthesizer operating from 8 to 12.4GHz suited for data communication standards. The synthesizer generates a low noise clock with rms jitter of 288–460fs, yet maintains wide loop bandwidth from 1.5 to 4.3MHz. The design consumes 16.9mW from a 1V supply, while occupying an area of 0.39mm2 in a 40nm CMOS technology.
This paper presents an ultra low power reconfigurable, multi-standard (IEEE802.15.4, BLE, 5Mbps proprietary) ISM2.4GHz band transceiver compliant to FCC, ETSI class 2 and ARIB regulations. It uses a DPLL with counter based area and power efficient re-circulating TDC, current reuse low area DCO, dynamic divider, class-AB PA, and fully integrated LDOs. The RX is reconfigurable between zero-IF/low-IF...
Over the past five years, we have seen the evolutionary growth of smartphones and tablets. These mobile devices have revolutionized our lives with cutting edge semiconductor and display technologies that play key roles in data processing, communication, multimedia, graphics and imaging as well as display. This paper will describe the path that mobile devices have walked along and provide some perspectives...
A wideband receiver back-end supporting dual band reception for carrier aggregation has been implemented in 32nm CMOS. The proposed architecture relies on tunable phase generation circuitries, feeding parallel paths consisting of a harmonic rejection mixer and a ΔΣ-ADC. 3rd and 5th order harmonic distortion is suppressed through statistical calibration, exploiting the inherent circuit variability,...
We have realized the characterization of MOSFET noise up to 3 GHz by locating a low-noise (LN) transimpedance amplifier (TIA) close to the devices to be tested (DUTs). A noise floor as low as 3 pA/vHz was achieved by using an external high-voltage input. Moreover, a high-frequency noise probe equipped with a TIA IC was fabricated, with which measurements in a frequency range up to 800 MHz were achieved...
While CMOS downscaling approaches its limits, ESD protection design is facing significant challenges. Technology measures which facilitate further technology scaling enhance the sensitivity of the devices against ESD stress. At the same time demanding performance requirements more and more limit the options of circuit solutions for ESD protection. In consequence ESD qualification goals for ICs had...
As technology has advanced, layout dependent device parameter shifts are becoming more influential to the actual circuit operation and performance, such that design style differences could create systematic device variability due to layout unless those effect are minimized and well captured in the device model[1]. In this paper, we characterize the device layout effects on a high performance planar...
For the first time a full hybrid integration scheme is proposed, allowing a full circuit design transfer from 28nm Bulk CMOS high-k/metal gate onto UTBB FDSOI with minimum design effort. As the performance of FDSOI logic and SRAM devices have already been reported, this paper highlights the original way to integrate ESD devices, variable MOS capacitors and vertical bipolar transistor within the frame...
An 820-GHz 8×8 imaging array using diode-connected NMOS transistor detectors is demonstrated in 130-nm CMOS process. Measured mean responsivity of 3.4 kV/W and mean NEP of 28 pW/Hz1/2 at 1MHz modulation frequency are achieved. The NEP is 3.5X lower than that of NMOS and slightly lower than that of Schottky diode terahertz imaging arrays implemented in CMOS. The minimum NEP is 15.5 pW/Hz1/2, which...
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