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This paper presents a 160GHz center frequency pulsed transmitter for short range radar applications. An array of four transmitters was implemented in a single chip with antennas implemented on the package. Each transmitter can be independently phase shifted, allowing transmit beamforming. The implemented transmitter is capable of producing pulses of 100ps wide (>20GHz RF bandwidth) with 160GHz...
A 1-inch optical format, 14.2M-pixel, 80fps, digital-output CMOS image sensor that employs a row-shared dual conversion gain pixel is presented. To achieve the 80 fps readout rate, a pipelined pixel reset/readout scheme named “nesting scan” has been introduced, where the charge sense node inside a pixel is reset during the previous row. Readout noise and maximum handling signal charge of the sensor...
A high-speed, low-power pipeline ADC is realized by replacing the front-end residue amplifiers with pulsed bucket brigade circuitry and compensating for the introduced errors using digital linearization. The ADC is implemented in 65-nm CMOS and occupies 0.26 mm2. It operates at 200 MS/s, consumes 11.5 mW from a 1-V supply and achieves an SNDR of 65 dB at low input frequencies and 57.6 dB near Nyquist...
A ternary content-addressable memory (TCAM)-based hardware called nonvolatile “multi-functional CAM (MF-CAM)” is proposed for an ultra-low-energy “full-text search” system in recent data centers. The proposed nonvolatile MF-CAM-based full-text search engine can perform parallel comparison while eliminating leakage energy by hierarchical power gating. By the massively parallel comparison with the hierarchical...
A 1Tbit/s bandwidth PHY is demonstrated through 2.5D CoWoS platform. Two chips: SOC and eDRAM have been fabricated in TSMC 40nm CMOS technology and stacked on another silicon interposer chip in 65nm technology. Total 1024 DQ bus operating in 1.1Gbit/s with Vmin=0.3V are proven in experimental results. A novel timing compensation mechanism is presented to achieve a low-power and small area eDRAM PHY...
We developed an ultra-low noise image sensor in which an organic photoconductive film (OPF) is laminated on the entire surface of the pixel circuits. In order to suppress the kTC noise in the pixel circuit of a three transistor configuration, a high-speed column feedback noise cancel circuit is newly developed. An ultra-low noise of 2.9 electrons during the horizontal blanking period of only 5 µs...
A 3D IC heterogeneous chip integration of 65nm RF receiver, 28nm baseband processor, and 40nm DRAM on a proprietary CoWoS structure is demonstrated and its electrical characterization of KGS (Known Good Stack) has revealed a highly comparable system performance as compared to that of the KGD (Known Good Die) testing data. Moreover, an innovative system BIST (Built-in-Self-Test) scheme and methodology...
3D Integrated Circuit (3D-IC) opens architecture opportunities for improved SoC-to-memory interconnect bandwidth between dies. This paper presents the design of a two-tier 3D-IC composed of one NoC-based MPSoC and one multi-channel WideIO mobile SDRAM stacked in a face-to-back configuration. Measurements of the 3D-IC show that the targeted 12.8 GByte/s bandwidth is achieved in worst case conditions,...
An integrated lab-on-chip capable of performing quantitative polymerase chain reaction (qPCR) is demonstrated in a high-voltage 0.35-µm CMOS process operating at a 3.3 V supply. PCR thermal cycling can be performed by physically moving droplets between three distinct temperature zones on the surface of chip or by thermal cycling a droplet in place. Droplet actuation is enabled by electrowetting-on-dielectric...
Large-area electronics (LAE) enables diverse transducers on large, flexible substrates (∼10m2), making possible expansive sensor arrays and energy harvesting devices. We present a second-generation system for high-resolution structural-health monitoring of bridges achieved by combining LAE with CMOS ICs in a scalable architecture. It aims to enable strain sensing scalable down to cm-resolution over...
In this paper, an integrated pulse wave velocity (PWV) sensor that adapts ECG and Bio-impedance (BI) method is proposed. PWV is calculated by measuring the time-difference between the signals from ECG sensor on chest and BI sensor on wrist. To gather these two signals without any cumbersome wires over the body, a noise-shaped body-channel communication method using analog frequency modulation is proposed...
The Symposium on VLSI Circuits is sponsored by the Japan Society of Applied Physics and the IEEE Solid-State Circuits Society, in cooperation with the Institute of Electronics, Information and Communication Engineers of Japan.
An integer-N digital PLL architecture is presented that simplifies the critical phase path using a sub-sampling binary (bang-bang) phase detector. Two power-efficient techniques are presented that can reduce DCO frequency tuning step by voltage-domain and time-domain (pulse-width) modulating the DCO LSB varactors. Measurement shows 210fs RMS jitter at 11.8GHz DCO frequency and 6mW power.
A single-chip HEVC (H.265) 8192×4320p encoder is implemented on a 25mm2 die with 28nm process. It dissipates 708mW at 312MHz for 8192×4320p encoding. Frame-level pipelining reduces 8.90 GB/s external memory bandwidth and improve CABAC rate by 50%. A 7.14MB three-level memory hierarchy is designed to support internal 43.38 GB/s bandwidth and 13-port accesses, and reduces external reference frame bandwidth...
This paper presents a fully-integrated bidirectional SC ladder converter in 0.13µm 1.2V/3.3V triple-well CMOS with peak output voltage of ∼10V. The converter actively drives a 5nF mm-sized piezo-electric robotic wing while following <500Hz arbitrary waveforms at ∼3x step-up conversion. High voltage drive signals for the power switches are developed using a new voltage-distributed nested-bootstrapping...
This paper presents a high performance and highly reliable SRAM realized by collaboration between advanced FinFET device and circuit technology. As for the device technology, the amorphous metal gate FinFET with the record smallest AVt value (=1.34 mVµm) are demonstrated. As for the circuit technology, it is demonstrated that both reliability and performance of SRAM are dramatically enhanced by introducing...
We propose for the first time a complete SRAM offer in FDSOI technology, covering low leakage, high speed and low voltage customer requirements, through simple and innovative process/design solutions. Starting from a bulk-design direct porting, we evidenced +50% and +200% bead at Vdd=lV and 0.6V, respectively vs 28LP bulk. Additionally, −100mV Vmin reduction has been demonstrated with 28FDSOI. Alternative...
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