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A 1Tbit/s bandwidth PHY is demonstrated through 2.5D CoWoS platform. Two chips: SOC and eDRAM have been fabricated in TSMC 40nm CMOS technology and stacked on another silicon interposer chip in 65nm technology. Total 1024 DQ bus operating in 1.1Gbit/s with Vmin=0.3V are proven in experimental results. A novel timing compensation mechanism is presented to achieve a low-power and small area eDRAM PHY...
This paper presents a novel 1Mb STT-MRAM for power and area reduction of cache memory in micro-processors. This memory adopts current-integral sensing scheme for high speed read, and uses advanced perpendicular STT-MRAM for high speed write to achieve 250 MHz operation, 17.8 mW read power and 46.5 mW write power per 256-b I/O. Using a processor simulator, it has been confirmed the total cache power...
We propose a new top-pinned perpendicular MTJ structure that can both achieve the magnetic stability of a pinned layer and reduce a magnetic stray-field to a free layer. The key point of the structure is that there is a large design margin of a pin configuration for the stray-field reduction due to a counter bias magnetic field layer being used instead of a SAF structure. Stable switching performances...
We propose and demonstrate a dynamic self-adaptive write method (DSWM) for the first time, which fixes the reliability problem that over-set or over-reset degrades ReRAM endurance and retention of tail bits significantly. The demonstration is carried out on a 128Kb test macro of AlOx/WOx bi-layer ReRAM fabricated based on 0.18µm standard logic Al interconnect. Results show that the mean value of endurance...
We demonstrate a novel p-channel 3D stackable NAND Flash that uses completely new programming and erasing methods. The p-channel 3D NAND avoids the disadvantage of GIDL induced hole erase of floating body n-channel NAND, giving a highly efficient -FN hole erasing and negligible disturb on the SSL and GSL devices. The p-channel NAND structure enables a novel -FN erase selection method, providing a...
Multi-level cell (MLC) programming is of crucial importance to make a cost competitive NAND Flash product. In conventional 2D floating gate NAND Flash, the interference and disturb become very severe as technology scales, and many methods have been adopted to alleviate the interferences. In 3D NAND, the pitch is generally larger and the charge-trapping device naturally has smaller interference. However,...
3D vertical RRAM scaling limit is investigated. 3D RRAM functionality along with a viable write/read scheme for the 3D array are experimentally demonstrated for the first time, using plane electrode with thickness (tm) down to 5 nm to minimize 3D stack height. Through 3D circuit simulation of the write/read margin, we conclude the practical lower bound for the lithographic half-pitch, F, is 26 nm...
During the last few years there has been an explosive growth in demand for smartphones with increasing capabilities and performance. With this demand come many associated hardware challenges.
A BEOL-process-compatible, high-voltage complementary MISFET inverter formed on Si-LSI Cu-interconnects (hereafter we call BEOL-CMOS, Fig. 1), is presented for the first time. High Ion/Ioff ratio N-type IGZO and P-type SnO dual oxide semiconductor channels are integrated to form BEOL-CMOS logic with just two mask addition to the state-of-the-art BEOL process (Figs. 2 and 3). BEOL-CMOS flow is developed...
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