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Dual Work Function (DWF)-MOSFET of 100 nm gate length device with self-aligned integration scheme was demonstrated utilizing conventional CMOS platform process for the first time. Here, we obtained not only the improved transconductance (GM) and drain conductance (GD), but also the enlarged operation voltage window employing multi gate oxide structure combined with DWF gate stack. Also, the discriminative...
To satisfy strict requirements of storage-class memory, a bipolar TaOx/TiO2 RRAM has been developed. Numerous highly desired features, including: (1) extremely high endurance over 1012 cycles, (2) forming free, (3) self compliance, (4) self rectification ratio up to 105 required for ultrahigh-density 3D vertical RRAM, (5) multiple-level-per-cell capability, (6) room-temperature process, and (7) fab-friendly...
A new read method which suppresses the effect of read current fluctuation due to random telegraph noise was proposed to reduce read error in NAND flash memory by using hysteretic characteristic. By controlling the amplitude and polarity of a word-line (WL) bias applied to the gate of a selected cell in a cell string, we can predict stochastically RTN event at μsec time range. From measured transient...
On behalf of the organizing committee, we would like to welcome you to the 2013 Symposium on VLSI Technology in Kyoto, June 10–13, 2013, jointly sponsored by the Japan Society of Applied Physics and the IEEE Electron Device Society. The Symposium on VLSI Technology has long been recognized as one of the premiere technical conferences showcasing the latest advancements in semiconductor technology,...
We have realized the characterization of MOSFET noise up to 3 GHz by locating a low-noise (LN) transimpedance amplifier (TIA) close to the devices to be tested (DUTs). A noise floor as low as 3 pA/√Hz was achieved by using an external high-voltage input. Moreover, a high-frequency noise probe equipped with a TIA IC was fabricated, with which measurements in a frequency range up to 800 MHz were achieved...
The ever increasing stress engineering raises a major concern of strong layout-dependent effects (LDE) in the advanced technology nodes. We report on the dependency of SiGe S/D and STI induced stress on fin length, position of the gate along the fin and fin to fin distances. The efficiency of epitaxial S/D SiGe stressors is reduced when the fin length is decreased and strongly degraded for fins with...
Double-patterning lithography is required at 20 nm node for planar CMOS. At the 16 / 14 nm node, in order to deliver attractive amount of Performance-Power-Area enhancement, 3-D FinFETs are required. Close collaboration at design ecosystem among fabrication foundry, EDA vendors, IP vendors, packaging vendors, and design houses is crucial for successful migration to FinFET circuits. This paper describes...
As technology has advanced, layout dependent device parameter shifts are becoming more influential to the actual circuit operation and performance, such that design style differences could create systematic device variability due to layout unless those effect are minimized and well captured in the device model[1]. In this paper, we characterize the device layout effects on a high performance planar...
A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency...
This paper presents the implementation details and silicon results of a 2.6GHz dual-core ARM Cortex A9 manufactured in a 28nm Ultra-Thin Body and BOX FD-SOI technology. The implementation is based on a fully synthesizable standard design flow, and the design exploits the great flexibility provided by FD-SOI technology, notably a wide Dynamic Voltage and Frequency Scaling (DVFS) range, from 0.6V to...
While CMOS downscaling approaches its limits, ESD protection design is facing significant challenges. Technology measures which facilitate further technology scaling enhance the sensitivity of the devices against ESD stress. At the same time demanding performance requirements more and more limit the options of circuit solutions for ESD protection. In consequence ESD qualification goals for ICs had...
For the first time a full hybrid integration scheme is proposed, allowing a full circuit design transfer from 28nm Bulk CMOS high-k/metal gate onto UTBB FDSOI with minimum design effort. As the performance of FDSOI logic and SRAM devices have already been reported, this paper highlights the original way to integrate ESD devices, variable MOS capacitors and vertical bipolar transistor within the frame...
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