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In this study, a reduction in the saturation current caused by self-heating effect at high VGS is observed in a 35-V rated asymmetric DEMOSFET. The high VGS -induced the large current and raises up the device surface temperature. The Kirk-effect takes places at sufficiently high current levels (high VGS values) leading to the movement of the maximum temperature point from the gate-overlapped DE (drain-extended)...
The purpose of this study is to clarify the more reliable design for ONO Gate insulator film for Trench Gate MOSFET. Partially Thick Oxide Trench Gate MOSFET (PTOx-TMOS) with ONO Gate film can reduce the Ron*Qgd Figure of Merit on easy process and simple structure. However this structure is required the appropriate design to prevent threshold voltage shift originated in charge storage effect. In this...
This paper discusses a circuit simulation model for interdigitated source LDMOS. As p+ well contacts are inserted to the source regions, the device achieves high breakdown immunity without using high voltage p+ implantation under the source. However, since the parasitic resistance near the source p+ region is not formulated in the conventional compact model, the accuracy of the model is an issue....
Power electronic interfaces are vital to advanced, smarter, distributed grids and micro-grids and the capabilities and limitations of power devices are integral to this. This paper discusses existing and emerging applications of grid connected electronic interfaces that are enabled by Power Semiconductor Devices. The application focus will be on: (1) inverters, which are a key element of modern distributed...
Power electronic semiconductors from the viewpoint of an automotive OEM. Improving efficiency, especially in the “hidden” utilization of power electronic semiconductors, defines the next level of automotive electrification. AUDI breaks new ground in the semiconductor industry by strongly influencing the future of power electronics. Next to new products and functions, new forms of collaboration, networks...
It is confirmed that more electric society is right direction toward sustainable growth achievement. Electronics including power electronics which enables efficient energy usage is important key technology for the society. Nega-watt cost concept, as an index of development, is proposed to promote efficiency improvement and prevalence of the next generation power electronics (PEs). Improvement of power...
On behalf of the ISPSD conference committee, it is with great honor and pleasure that I welcome you to the 24th International Symposium on Power Semiconductor Devices and ICs (ISPSD'12). ISPSD is the premier forum for technical discussion in all areas of power semiconductor devices, power integrated circuits, their hybrid technologies, and applications. This symposium brings together both industry...
A PNM (Partially Narrow Mesa) -IGBT with a fundamentally new surface is proposed for the first time. The unique gate shape looks like a “vase” and generates an extreme injection enhancement. Its performance approaches the limits of Si-IGBT. Therefore, PNM-IGBT is able to contribute to the saturation voltage reduction and the improvement of Vce(sat)-Eoff trade off. Furthermore, it can be adapted to...
A sensefet monitoring is used for overload, open-load detection and load current analog feedback. The sensefet matching properties to the main power mos represent the main quality factor of the device. Its current should be proportional to the main power one, maintaining the same coefficient over the entire temperature and biasing working range. In this work the effects of the edge cells layout and...
This paper presents BCD process integrating 7V to 70V power devices on 0.13um CMOS platform for various power management applications. BJT, Zener diode and Schottky diode are available and non-volatile memory is embedded as well. LDMOS shows best-in-class specific Ron (RSP) vs. BVDSS characteristics (i.e., 70V NMOS has RSP of 69mΩ-mm2 with BVDSS of 89V). Modular process scheme is used for flexibility...
This work reports the hot-carrier (HC) behavior and specific on-resistance (Ron,sp) optimization of 20∼60 V p-channel LDMOS transistors implemented in a 180 nm HV-CMOS technology. By precise control the implant dose and energy of a p-drift region, which is surrounded by n-type isolation well, one can efficiently optimize the on-resistance and breakdown voltage (BV) trade-off while keeping very low...
A novel HV thin layer SOI technology based on 1.5-µm-thick silicon layer for negative HV power supply has been first proposed. HV field nLDMOS with thick gate oxide, HV pLDMOS with thin gate oxide and LV CMOS are compatible with shallow trench isolation. Gate and source field plates are adopted to improve the breakdown characteristics of HV field nLDMOS since it doesn't meet SOI RESURF criterion....
A 4.5-kV voltage level-shift circuit with a multi-chip structure composed of upper and lower arm driver ICs and dedicated discrete IGBTs was developed. It was experimentally confirmed that this level-shift circuit could drive a 3.3-kV/1200-A IGBT module.
A novel double-well (DW) divided RESURF isolation structure featuring two slender N-Well regions at N−-Well, aiming at improving the off-state breakdown voltage for high voltage IC (HVIC) is proposed in this paper. The N-Well regions in the presented structure efficiently prevent N−-Well which used for the drift region of the Lateral Double Diffused MOSFET (LDMOS) from depleting with P-Well, so as...
We have established the 700V-class PIC technology based on 0.35µm design to provide power management ICs with higher performances and lower chip cost for the first time. And a 700V PWM-IC based on 0.35µm design, whose chip size can be reduced to 50% that of the IC based on 1.0µm design, is realized. This paper will report our developed 700V PIC technology with a PWM-IC product designed by this technology.
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