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Durability of IGBT modules mainly depends on reliability of the thick Al wire bonds used in them. We investigated the reliability of thick Al-0.5mass%Mg2Si wire bonds in comparison with conventional Al-50ppm Ni wire bonds. The shear strength of both Al-0.5mass%Mg2Si and Al-50ppmNi wire bonds were measured as a function of the number of thermal cycle tests. The strength ratio of Al-50ppmNi wire bonds...
High power compact IGBT half bridge modules with a current rating of 300A and a blocking voltage of 650V using ultra thin IGBTs and diodes have been successfully developed with double-sided cooling capability. The wirebond-less package building block called COOLiR2DIE™ has a small area of 28.5 mm × 16 mm with a power rating 200 kVA, This is the most compact IGBT package reported today. A low on-state...
We have proposed and fabricated AlGaN/GaN HEMTs employing a nickel oxide (NiOX) based double metal structure which showed a stable reverse blocking characteristics. The leakage current of the proposed device was decreased by four orders of magnitude. The leakage current of the conventional device at room temperature was 80 µA/mm while that of the proposed device was 16.6 nA/mm. In the high temperature...
Silicon Carbide (SiC) is a good candidate for high temperature power electronic applications. To ensure good reliability, packaging materials with a coefficient of thermal expansion (CTE) matching that of SiC are needed. A metallized ceramic substrate based on aluminium nitride (AlN) and molybdenum (Mo) is reported in this paper. This substrate is built using a spark plasma sintering equipment. Results...
The power losses in System-in-Package (SiP) 12V-input DC/DC buck converters with advanced 30V Shield-Plate FETs (SP-FETs) are assessed by experiment and simulation with special interest in the body-diode contribution. Unlike previous work, rise/fall times and on/off deadtimes are in the nanosecond range to provide high efficiency at high frequency operation (1–4MHz).
Monolithic integration of RC snubbers in power electronic applications offers great opportunities. The presented devices provide tight tolerances and enable high integration densities. Especially, the incorporation into power modules enables reduction of electromagnetic interferences in accordance with reliable lifetime predictions.
In this paper, a planar silicon-oxide-nitride-oxide-silicon (SONOS) gate power MOSFET (SG-MOSFET) with a 0.3 µm ultra-shallow heavily doped p-body region is presented. The ultra-shallow body provides a much reduced parasitic JFET resistance, resulting in a low specific on-resistance of 18 mΩ·mm2 for a planar device. At the same time, no punch-through problem is caused by the ultra-shallow body, and...
In this paper we present the detailed investigation of the influence of the internal bipolar PNP transistor gain on the thermal stability of high voltage IGBTs and BiGTs. The bipolar gain is controlled by means of anode and buffer design and by the introduction of anode shorts. The influence of the different buffer and anode doping profiles and the different layouts in the case of anode-shorted designs...
In this paper, we report the experimental results of a 3.3kV rated CIGBT (Clustered Insulated Gate Bipolar Transistor) with planar gates in non-punch through technology (NPT) with RTA anode. Previously it was reported that for identical turn-off losses the on-state voltage of the 3.3kV NPT-CIGBT is less than 0.7V as compared to that of a commercially available FS-IGBT. Herein we show that due to the...
In this paper, we present the characteristics of a fabricated 600V CSTBT™ as the next generation IGBT. The techniques applied this novel device include about half-size shrinkage of the transistor unit cell with a fine pattern process and an LPT (Light Punch Through) structure utilizing an advanced thin wafer process technology. As a result, these techniques brought a significant reduction of the Vce(sat)...
The aim of this paper is to analyze the typical voltage and current waveforms of UIS test in order to find signature of uneven current conduction behavior. This information could help the identification of phenomena that can eventually lead to device failure, reduce its capability of sustaining high currents in avalanche operation or impair long-term device reliability.
Deep trench gate is used for latest IGBT to improve device performance. By large difference from deep submicron CMOS structure, there is no process compatibility among CMOS device and trench gate IGBT. We propose IGBT scaling rule for shrinking IGBT cell structure both horizontally and vertically. The scaling rule is theoretically delivered by structure based equations. Device performance improvement...
In this paper, we investigate a mechanism of drain-voltage oscillation of MOSFET under high dV/dt UIS condition by using numerical simulation and experiments. One of the trigger events of the oscillation is found to be the current path switching between the active region and the termination region with close BVDSS characteristics. By optimizing the device parameters to make appropriate the BVDSS balance,...
The paper presents current technological achievements and associated characterizations of the mechanical, thermal and electrical properties of the assembly at wafer level of vertical power devices matrices. Based on direct bonding technology, metallic substrates are bonded to the Silicon active layer at wafer level to ensure back-side common electrode electrical interconnections while offering outstanding...
A novel silicon device architecture for DC-DC power conversion is reported. Efficient switching at high frequencies (1–5 MHz) is achieved by simultaneously reducing gate charge, reverse capacitance, and gate resistance while still maintaining good on-state resistance and off-state breakdown voltage. Power efficiencies in excess of 88% were realized in a synchronous buck converter running at 1.3 MHz.
A novel JFET redesign of a laterally scaled P-LDMOS device is presented. The P-LDMOS device has excellent Rsp as it is scaled from 90V to 170V operation. This P-LDMOS design is modified to produce a 100V PJFET with good turn-off characteristics and a relatively low Vpinch of 3–7V.
In this paper we present a mechanism leading to early fails in a trench power MOSFET when operated at high drain currents under repetitive avalanche conditions (also referred to as “unclamped inductive switching”). While typical fails show burn marks at (or under) the bond stitches, early fails can occur close to the active area's edges or corners. With plausible assumptions both cases can be consistently...
Power converters, e.g. in a popular synchronous buck topology, need high performance power MOSFETs in order to achieve high efficiency, low voltage ringing, ESD protection and low EMI. To satisfy these requirements, an asymmetric gate resistor power MOSFET is proposed by integrating a shunt resistor with a parallel LDMOSFET-connected diode in a source down power MOSFET (NexFET). The novel MOSFET has...
This paper presents a 20V-rated planar dual gate oxide NLDMOS power device structure fabricated in a 180nm power management technology. The performance of the planar dual gate device structure is compared to a conventional STI-based device and it is shown that the planar dual gate structure has superior BVds-Rsp, gm, HCI reliability, and forward safe operating area figures-of-merit. The planar dual...
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