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Considering the pervasion of wireless portable devices and growing trends in the use of multimedia applications, access to a high speed and, especially, a high throughput wireless channel are of significant importance. In addition to security concerns in wireless devices, deficiency in throughput and also increase in power consumption are introduced to the system by applying security. Therefore, designing...
Energy consumption in sensor network is one of the most important goals in designing a routing protocol. An energy efficient routing protocol will decrease number of transmitted and received packets, because main consumption part in routing is using antennas and signals. This paper presents an energy efficient routing protocol, called Remaining-Energy Based Routing (REB-R). The idea behind REB-R is...
The structure of direct vertical interconnections, called Through Silicon Vias (TSVs), is an important issue in the realm of 3D ICs. The bus-based and network-based structures are the two dominant architectures for implementing TSVs as interlayer connection in 3D ICs. Both implementations have some disadvantages. The former suffers from poor scalability and deteriorates the performance at high injection...
Advances in CMOS-compatible photonic elements have made it plausible to exploit nanophotonic communication to overcome the limitations of traditional NoCs. In this paper, we consider buffer management as a resource allocation which can be cast as a convex optimization problem. Using this framework enables us to devise a token-based optimal buffer management algorithm in optical on-chip architecture...
In this paper, a simulation-based fault injection analysis of a MIPS-based dual-core processor is presented, an approach is proposed to improve the reliability of most vulnerable parts of the processor components and then the improvement is evaluated. In the first series of experiments, a total of 9100 transient faults were injected in 114 different fault sites of the processor. These experiments...
Increasing delay and power variation has become a major challenge to designing high performance Multiprocessor System-On-Chips (MPSoC) in deep sub-micron technologies. As a result, a paradigm shift from deterministic to statistical design methodology at all levels of the design hierarchy is inevitable. In this paper, we propose a static variation-aware task scheduling and power mode selection algorithm...
Currently few architectural approaches propose new paths to raise the performance of conventional sequential instruction streams in the time of the billions transistor era. Many application programs could profit from processors that are able to speed up the execution of sequential applications beyond the performance of current superscalar processors. The Grid Alu Processor (GAP) is a runtime reconfigurable...
As the demand for more data storage space continues to grow at an unprecedented pace, the need for real time data compression systems becomes more prominent. One of the well-known methods among lossless data compression algorithms is LZW. In this paper, a new prediction algorithm has been introduced that is able to predict whether or not a data block is compressible with the LZW method. Furthermore,...
In this paper, a low-cost 3D NoC architecture based on Bidirectional Bisynchronous Vertical Channels (BBVC) is proposed as a solution to mitigate high area footprints of vertical interconnects. Dynamically self-configurable BBVCs, which can transmit flits in either direction, enable a system to benefit from a high-speed bidirectional channel instead of a pair of unidirectional channels for inter-layer...
The limited memory space of caches are used in unbalanced way, which generate more conflict misses in some sets while other sets are underutilized. We propose a technique using the tag of address through Hash Functions to address the most underutilized sets in the cache to replace. Therefore, conflict misses in the cache can be resolved by distributing accesses along cache sets evenly. In comparison...
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