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An untrimmed pipelined 8-bits A/D converter with both integral and differential nonlinearity error less than 1Lsb is presented. At clock frequency of 3Mhz, the circuit achieves a 1.5Msample/s data rate. Power consumption is 20mW and chip area is 2 mm2 in a 3????m CMOS technology.
This paper presents a monolithic 20 bit analogue to digital converter. The converter is implemented in a standard 2??m N-well CMOS process and requires 14 mm2 including the pads. Measurement results are presented which demonstrate the feasibility of a converter with 20 bit absolute accuracy. The complete converter has a power consumption of 6.7 mW.
This paper describes the design and evaluation of a 1.4GHz clock rate monolithic digital delay generator. The application area for the device is in digital radio frequency memories (DRFM).
This paper deals with the combination of a powerful 16b microcontroller and a high precision signal acquisition unit. Traditionally, a digital technology, a fast, complex processing unit and precise analog signal handling have been regarded to be incompatible. For the first time a true 10 channel 10 bit A/D converter capable of handling analog signals up to several 100 kHz and with a total unadjusted...
This paper describes VLSI architectures for multiplication modulo p, where p is a Fermat prime. With increasing p, ROM based methods become unattractive for integration due to excessive memory requirements. Two new methods are discussed and compared to ROM implementations with regard to their speed/complexity behaviour. The first method is based on a (n + 1) x (n + 1) bit array multiplier, the second...
The paper first introduces a novel machine paradigm as a model for very high performance implementation of parallel algorithms in important application areas such as image processing, digital signal processing, computer graphics, VLSI layout verification, routing and others. The paper illustrates this model by means of a simple application example. Then the paper introduces a novel method for fast...
A high speed Analog-Digital converter realized with a standard Bipolar process (Ft = 8 GHz) is presented. Optimized design and novel layout concept of the chip, leads to operating frequency up to 1 GHz sampling rate with less than 1.4 W power dissipation. The architecture and the design of the main functions are described. The way to optimize dynamic performance is shown in the paper. Main measurement...
A 130 MHz CMOS video DAC with a current output for HDTV applications will be described. In order to achieve monotonicity and a high speed performance,a current cell matrix configuration and a parallel decoding circuit with one stage latches have been used. P channel devices used as current sources insure a low noise level and a ground referenced voltage output in double adaptation load (38 ohms /...
A silicon compiler has been produced which, from a short textual specification containing values of critical parameters, produces mask details for a particle counting chip. Initially it has been applied to a specific CMOS architecture having three distinct regions; a two-dimensional array of sensitive electrodes with associated amplifiers and comparators, RAM for accumulating data and a controller...
A technique is presented to derive all the control signals needed for focusing and radial tracking in a digital servo system for CD-players, as well as the full-band data, with multi-bit ΣΔ A/D converters. The ΣΔ approach is of great interest because of its suitability to integrate in a VLSI process and no anti-aliasing filter is required due to the oversampling technique.
The role of CAD Tools and Systems for the design of integrated circuits is nowadays critical for the success of the design activity. IC manufacturers consider today CAD technology as important as process technology due to the impact of CAD and design automation on the productivity of the designer community and on the capability of exploitation of what silicon technology can offer. The tighter and...
This paper discusses the interactions and trends between algorithms, architectures and technology for high performance digital signal processing integrated circuits. It is shown how with current techniques processing throughput rates in excess of 5000MOps are readily achievable in single chip.
This paper describes the architecture and key circuit techniques of a PSRAM using the BiCMOSG3 cell for storage array. The important features of the cell from the circuit techniques point of view are reported. An inverting refresh scheme resulting in a very simple refresh circuitry is proposed. The functional separation between refresh amplifiers and sense amplifiers for selective access operations...
This paper describes a 4K??16 Dual Port Memory. The component is designed with the .8um 1 polysilicide / 2 metals MHS' SCMOS technology and it has a full CMOS 8-transistor-memory cell. It has been designed in order to fit requirements such as military specifications and compatibility with market demand. The internal circuits and floor-plan are organized to obtain enough flexibility for designing other...
A new technic called cyclic Auto-zero is presented. The realization of 10 bits 20 MHz flash CMOS ADC based on this technic is described. Results of this circuit are presented at the end.
VLSI design productivity quests for an efficient design system, incorporating testability features. Usually, design for testability (DFT) techniques are applied down to the logic design level, and test patterns are generated to cover single line stuck-at (LSA) faults. However, for CMOS technologies, this fault model is not sufficiently acccurate. In this paper, a methodology for extending and assessing...
A prototype chip implementing a 7-th order pole-zero low-pass digital LDI ladder filter with programmable coefficients has been fabricated in 1?? CMOS technology. Its complexity is 17000 transistors, with an area of 3 mm2. This circuit was designed as a test vehicle for a fully integrated VLSI function compiler, that takes as input the frequency specifications of a filter. New and unique LDI structures...
A CORDIC processor for vector rotations using a carry-save architecture has been developed and realized. The CORDIC algorithm is based on an iteration, directed by the sign of intermediate results. To achieve a high clock frequency of 60 MHz the CORDIC iteration was built up with pipelined carry-save adder stages. Due to the redundant number representation of the carry-save architecture an exact sign...
A high frequency very low distortion transconductor is introduced. The Total Harmonic Distortion (THD) is lower than -60 dB's for a differential input voltage of 2.4 Vptp (Volts peak to peak), which represents 41 % ofthe transconductor bias current. The dynamic range is in the order of 84 dB's. Furthermore, this structure presents low sensitivity to mismatches. The supply voltages are only +/- 2.5...
This paper describes two opamps and their applications. They have been processed in a 40 V BICMOS process. The low noise opamp combines a high input impedance with a thermal noise level of 8 nV/??Hz and a corner frequency of 100 Hz. The broadband opamp, also with high input impedance, shows a gain-bandwidth of 15 MHz with a load capacitance varying from 0 to 20 pF. A 4th order low pass switched capacitor...
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