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In asynchronous DS/CDMA systems, spreading sequences with appropriate negative auto-correlation properties can outperform conventional LFSR (linear feedback shift register) sequences with respect to bit error rate (BER) performance. Spreading sequences with negative auto-correlations can be generated by using one-dimensional chaotic maps but their hardware cost is more expensive than LFSRs. In this...
An integrated receiver channel for a pulsed time-of-flight laser rangefinder has been designed and simulated. Timing errors are minimized by using a resonance-based timing discrimination at the input of the receiver channel. The front end of the receiver has been implemented using CMOS transistors. The noise of the front end has been analyzed, optimized, and compared to earlier receiver channel realizations...
Spectrum sensing is one of the most challenging task in implementing future cognitive radios. The sensing unit should provide reliable information about the surrounding radio spectrum with small delay and low power consumption. This paper presents an implementation of a spectrum sensing unit capable of performing both cyclostationary feature detection and spectrum estimation for energy detection....
In this paper, we present the design and implementation of a tunable multi-band LNA for the mobile WiMAX (802.16e) standard using 0.13 mum CMOS process. The target frequency bands include 2.5~2.9 GHz, 3.4~3.6 GHz, and 5.2~5.9 GHz. The proposed LNA uses coupling capacitors to select frequency band. This technique leads to an improvement in linearity and frequency dependency of linearity as well as...
This paper presents an S band digitally controlled RF predistorter architecture suitable for power amplifiers operating in different traffic and load conditions. The developed digital controlled RF predistorter has enough control parameters and wide tunable complex gain range to make it adaptive and suitable to different type of power amplifiers such as TWTAs and SSPAs as well as driving signals....
In multi-rate digital receivers, analog to digital converter (ADC) mostly works at a fixed sampling rate. Subsequently, a sample rate conversion (SRC) process should be executed after the ADC to extract the desired baud rate. A polyphase decomposition comb filter is widely used as a first decimation stage in SRC circuit. In this paper, a power efficient clock/data distribution technique for the input...
Nowadays, the advances in the semiconductor industry allow to include a considerable number of fully digital processing elements on a chip. These massively parallel processor arrays are already able to host cellular wave computing algorithms with acceptable time performance. In this paper we approach the implementation of an originally CNN based algorithm for retinal vessel tree extraction on the...
This paper present two new low power, low noise UWB LNA utilizing a inter stage technique with a simple high pass filter and third-order passive Chebychev filter input matching network is proposed. The broad band matching and the flat gain are two important factors for the broadband circuits. Besides those factors, the minimal Noise Figure (NF) and the lower power consumption are also desired. The...
Switched reluctance motors (SRMs) are receiving significant attention from industries in the last decade. While switched reluctance motors have good performances, such as high torque, high speed, and high reliability, SRM has serious disadvantage of large torque ripple due to its the geometric characteristic, that is, saliency of the stator and rotor which causes undesirable acoustic noise and vibration...
This paper presents an 8-bit FPGA implementation of a discrete time cellular neural network (DTCNN) suitable for small image gray-scale pre-processing (simple operations with high computational burden). It uses Split&Shift techniques to have a 31 times 31 grid that processes more than 2500 images per second. As this work evolves from a previous binary DTCNN implementation, results are compared...
The most common wearout phenomena that impact reliability are: metal electromigration (EM), time-dependent dielectric breakdown (TDDB), hot carrier induced damage (HCID), negative bias temperature instability (NBTI) and thermal cycling. This paper focuses on electromigration and proposes two novel solutions. The first is the use of routing (or slotted) vias for improving electromigration performance...
With data rates reaching beyond the Gbps range, timing jitter has become a major limiting factor for todays highspeed communication systems. A novel decomposition algorithm is presented which accurately determines the impact of timing jitter on system performance. Based on collected jitter histograms, the method investigates Gaussian tail behavior of measured distributions and determines random and...
Modern advances in reconfigurable technologies are allowing analog circuit designers to benefit from the computational flexibility provided by large-scale field-programmable analog arrays (FPAAs). With the component density of these devices, small analog circuits as well as larger analog systems can be synthesized and tested in a shorter time and at a lower cost compared to the full design cycle....
This paper proposes a new second-order Model Order Reduction (MOR) method suitable for reducing very large sized RC circuits or RC circuit parts of a non-RC circuit. The MOR is carried out on a partitioned circuit, which enables the use of low-order moments and macromodels of few elements. It is shown that the use of the second-order MOR method in conjunction with lower-order methods improves the...
In this study, the synchronization of the master-slave systems has been achieved and implemented on Field Programmable Gate Array (FPGA). In this paper, the master system and the slave system have been chosen as Lorenz and Rossler systems, respectively. The feedback control rule has been derived by feedback linearization method. By feedback linearization, the coordinate transformation has been achieved...
An interface for integrated capacitive sensors producing a PWM signal is presented. The circuit is based on a recently proposed architecture, which is here improved by the introduction of a double clock strategy allowing jitter reduction. The non idealities of the circuit are investigated in order to obtain design criteria to reduce the jitter and the temperature dependence. The approach is validated...
In this paper, a new structure of voltage-mode MAX-MIN circuit is presented for fuzzy applications, neural network and etc. A differential pair with improved cascode current mirror is used to choose the desired input. The advantages of the proposed structure are high operating frequency, High precision, low power consumption, low area and simple expansion for multiple inputs by adding only three transistors...
This article presents a new second-order state variable filter including two amplifiers. The centre frequency of the resulting filter, f0, can be easily controlled using the gains of the amplifiers. This leads to a frequency-agile filter, whose centre frequency can be controlled over a wide range, without incidence on the power consumption. Simulation results given in this article confirm the new...
The IEEE WLAN 802.11a/g standard requires short time interval (5.6 mus) for automatic gain control (AGC) convergence during reception of the preamble in each data packet. Due to this stringent settling time requirement, most of the AGC is implemented after the baseband filter, which leads to high power consumption in the baseband filter. In this paper, we present syllabic companding using switched...
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