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This paper presents the design and fabrication of a radio-frequency (RF) transceiver fabricated in a UMC RF 0.18 mum CMOS process. The RF transceiver was built to operate at the 2.4 GHz ISM band. The receiver has a sensibility of -60 dBm and consumes 6.3 mW from a 1.8 V supply. The transmitter delivers an output power of 0 dBm with a power consumption of 11.2 mW. The application is a wireless wearable...
In this paper, we propose a power macromodeling technique for digital electronic circuits. This technique allows to estimate the power dissipation of intellectual property (IP) components to their statistical knowledge of the primary inputs/outputs. During power estimation procedure, the sequence of an input stream is generated using input metrics and the macromodel function is used to construct a...
High reliability requirements in many modern applications make soft errors an extremely important design aspect and pose new challenges in nanometer technologies. In addition, timing faults that may escape fabrication tests become a real concern in high complexity, high frequency designs. To confront this situation, a concurrent error detection and correction circuit and technique are presented in...
We develop a new method to compute representations of imprecise datapaths for purpose of equivalence checking and component matching. From a Taylor series, we devise an efficient algorithm to produce arithmetic transform (AT) which is a function representation behind word-level decision diagrams such as BMDs. Also, we introduce an efficient algorithm for verifying the imprecise circuits.
The design of a high speed, low voltage to high voltage level shifter in a digital 1.2 V, 0.13 mum CMOS technology is presented. The topology uses two differentially switched cascoded transistor ladders. The output signal has an offset of two times the nominal supply voltage of the used technology with respect to the input signal. Oxide stress and hot carrier degradation is minimized since all transistors...
The special ZXtalk method for completely degenerate interconnections (CDI) is capable of providing reduced echo and crosstalk in multiconductor interconnections, using few circuit elements. The paper defines the method and provides a design example showing how the termination circuits can be simplified. The paper also introduces a new type of MIMO amplifier, and explains why it is particularly suitable...
This paper deals with modeling, characterization and optimization of the analog front end (AFE) of a narrow band CENELEC power line communications modem. This study focuses on main lines and modem's AFE modeling to define analytical formulation of Modem insertion losses and line attenuations as functions of PLC modem coupling circuit's parameters. Experimental results of defined design review confirmed...
In this paper, a new approach that operates in the joint time-frequency domain for speech segmentation is presented. Segmentation is an important application in speech and audio processing. The segmentation in time domain is based on Renyi entropy especially on Renyi marginal entropy (RME) properties. Experiments were conducted using real-life speech signal as consonant-vowel (CV) transition that...
New analog circuits are presented to convert the output of a matched filter into symbol-and bit-likelihoods suitable as input to analog decoders for error correcting codes. The new circuits can be adapted to many constellations including pulse amplitude modulation (PAM) and quadrature amplitude modulation (QAM) and for arbitrary bit-to-symbol mappings. In contrast to a previously published circuit...
This paper presents a circuit/system level synthesis and optimization approach based on a learning scheme using support vectors machines (SVMs) and evolutionary strategies applied to the design of analog and mixed-signal ICs. This approach combines the best qualities of these two techniques, a robust classification and regression method and a powerful global optimization. The SVM is used to dynamically...
Pipelined ADCs with open-loop residue amplifiers are currently gaining designers' attention due to the simplicity of their design, their low-power and/or high-speed capabilities and their improved deep-submicron compatibility. Although several studies on power optimization of pipelined ADCs with closed-loop amplifiers are reported in literature, none so far addresses the power optimization problem...
A software correlation based detection method is designed for an FSK-profile modem for narrow-band communication over low-voltage power line networks. The correlator is designed to be suitable with a digitalization stage based on a simple comparator and to be simply realizable on a digital signal processor (DSP). Furthermore, the receiver calibration and its performances analysis in a white additive...
This paper presents some case-studies of an emerging nano-device, the carbon nanotube field-effect transistor (CNT-FET). First, we propose two design-oriented compact models, for both unipolar and ambipolar CNTFETs, i.e. devices with a classical behavior (MOSFET-like CNTFET) and an ambipolar behavior (Schottky-Barrier CNTFET). Models have been compared with exact numerical simulations and implemented...
This paper presents a very high-speed delta-sigma modulator for achieving digital generation of radio-frequency signals. About 68 dB of ACLR (adjacent channel leakage ratio) is obtained on the 7.8 GS/s output of the delta-sigma modulator for WCDMA standard. This is achieved by using original concepts like borrow-save arithmetic, non-exact quantization and differential dynamic logic.
In this paper, we represent sorting algorithm and operation procedure of a sorting network that is a "parallel sorter". This sorter has been programmed by "active-HDL" software and has been examined by "FPGA express" software for being able to be synthesized on FPGA chips. Due to using a structure almost like pipelining, input data and output data are independent of each...
This paper proposes a version of recursive least-squares lattice (RLSL) adaptive algorithm suitable for fixed-point implementation. It is based on a modified form of the cost function in order to obtain an asymptotically unbiased estimator of the mean-square error, reducing significantly the dynamic range of the algorithm's parameters. Moreover, in order to achieve an enhanced numerical accuracy an...
A leakage power minimization method in nanoscale CMOS circuits by transistor sizing in non-critical paths is presented. It is shown that a small increase in delay by transistor downsizing of non-critical paths can provide a significant reduction in leakage power. Moreover, nonlinear dependence of leakage current on width (due to inverse narrow width effects) can be exploited to minimize leakage power...
Digitisation of signals at RF imposes severe noise and linearity constraints. Furthermore, the drive towards integration with deep submicron CMOS process aggravates the difficulties in high frequency mixed signal circuit design. This paper first summarises the challenges in system and circuit facing GHz IF complex sampling. It then proposes a charge sampling receiver architecture which combines MEMS...
A 100 dB dynamic range global shutter CMOS image sensor implementing an innovative fixed pattern noise (FPN) reduction method is presented. This image sensor uses global shutter pixel architecture in order to avoid distortion in imaging fast moving objects. To limit shutter leakage, a new PMOS pixel architecture is implemented. The high dynamic range is reach through a logarithmic architecture pixel...
We describe in this paper a new method for the characterization and optimization with heuristic algorithm of fractional-N synthesizer. This method will be applied to GSM application. The treated synthesizer based in the use a type-II third order ΣΔ modulator generates signals in 935-960 MHz range with 200 KHz resolution with a spur of less than -80 dBc/Hz. Optimal parameters values are so determined...
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