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Target architectures for Simulink-based flows have been generally fixed and partitioned manually. The quality of the results or the final performance of the MPSoC depends heavily on the adaptation of the architecture to the needs in terms of processing performance as well as the efficiency of the communication protocols. The processing horse power determination is not limited to the selection of appropriate...
This paper presents an FPGA implementation of a high performance rank filter for video and image processing. The architecture exploits the features of current FPGAs and offers tradeoff between complexity and clock speed. By maximizing the operating frequency the complexity of the filter structure can be considerably reduced compared to previous 2D architectures.
Two highly linear, digitally programmable gain amplifiers (PGAs) are presented in this paper and compared in terms of linearity, frequency, area and power consumption. Both structures are characterized by their inherently high linearity and wide gain tuning range. Low distortion is achieved by means of an inherently linear MOST-only current division technique. A 3-bit prototype with constant bandwidth...
We present a method for BAW (bulk acoustic wave) filters computation. This method compares the equivalent impedance of the BUTTERWORTH-VAN DYKE (BVD) model based on an electrical equivalent circuit with the impedance obtained by piezoelectric equations in one dimension for a piezoelectric structure. Using the least squares method, the three elements of the BVD model can be determined as a function...
A low power successive approximation analog-to-digital converter is presented operating at 1.2 V supply. The circuit has been designed in a 0.13 μm standard CMOS technology. The power consumption while converting is 13 μW, and in standby mode the power is reduced to 5.8 μW. The resolution is programmable between 1 to 8 bits. It can work from 500 Hz up to 50 kHz clock frequencies.
A novel complementary quadrature LC oscillator is presented for achieving lower phase noise. One proposed and three conventional structures, designed in a 0.18 mum CMOS technology, are simulated in both the triple-well and the twin-well (exactly the quasi twin-well) process technologies and each phase noise is compared. These circuits operate at 5 GHz and draw 8.6 mA from a 1.8 V supply. In the triple-well...
Communication systems rely on stable VCO (voltage controlled oscillator) to maintain phase-locked conditions and ensure transmitted data integrity. Many third and later generation systems require multi-mode or multi-band signal sources (VCOs) to cover their bandwidth requirement. This paper presents the design of a dual-mode oscillator that simultaneously generates two signals at different frequencies...
This paper presents a novel approach to the design and post-layout simulation results of a low-voltage and low-power bandgap reference voltage in standard CMOS process. The proposed circuit makes use of a positive-and negative-temperature coefficient PTAT summed up to a resistive load to generate a low TC bandgap output reference voltage. Hspice-based simulations demonstrate that the reference circuit...
A concurrent dual-band low noise amplifier (LNA) for the 802.11a/g WLAN applications is presented. The circuit is designed in standard SiGe BiCMOS process from STMicroelectronics. The LNA circuit is a cascade topology with inductively degeneration transistor. A new input impedance matching network based on monolithic transformers was proposed to overcome to the problem of dual-band matching without...
We present is this article consistent guidelines to the design and implementation of fully-integrated BiFET low noise amplifiers (LNA). The effectiveness of BiFET topology and the applied methodologies are verified throughout measurement results of two fabricated BiFET LNAs. The first LNA is dedicated to W-CDMA applications (2.11-2.17 GHz) and its die area is 1.0 times 0.7 mm2. The second manufactured...
Hash functions are forming a special family of cryptographic algorithms, which are applied wherever message integrity and authentication issues are critical. As time passes it seems that all applications call for higher throughput due to their rapid acceptance by the market. In this work a new technique is presented for increasing frequency and throughput of the currently most used hash function,...
The era of nano technology and SOC's is driving the need for better and more compact design of embedded flash memories. This paper discusses circuit technique for a switched polarity 1.8 V charge pump based on Dickson's charge pump. The circuit can generate typical voltage levels for flash memories during both program and erase operations. The charge pump utilizes the same circuit elements to generate...
Speeding up FFT computations is critical for today's real time systems targeting signal processing and telecommunication applications. Aiming at the performance improvement and the efficiency of FFT architectures this paper presents an address generation technique which enables a b-radix processing stage to access in parallel b memory banks without conflicts and leads to increasing the speedup of...
A pulse modulator for ultra-wideband transmitters is designed and simulated using a 0.18-mum CMOS technology. 4-GHz carrier frequency is modulated into pulses with Gaussian envelop to push the spectrum to 3.1-5-GHz band. The transmitter brings low power operation due to digital structure, and high data transmission due to using I/Q modulation. The architecture of the modulator consists of Johnson...
In this work a CMOS neural processor is presented. Based on a mixed analog-digital architecture, the system processes data in analog current mode, using digital registers to store weights safely. The proposed processor consists of two main blocks: A mixed-signal four-quadrant multiplier and a class AB current conveyor that implements the non-linear output function. Achieved from the circuit-level...
In this paper, an optimization approach is presented to decrease the dark current in GaAs/AlGaAs QWIPs. Dark current noise, as shown, can be reduced by increasing Al density in barriers, decreasing detector dimensions and increasing the periodic length of the structure. It is also shown that increasing the number of periods can reduce both the dark current and responsivity. Therefore, devices can...
This paper presents on overview of the two chip integration of a digital radio receiver for wireless communication systems based on ultra wideband (UWB) impulse radio technology. The chips have been integrated in a 130 nm CMOS technology. The front-end performs 1-bit direct sampling of the RF signal. The baseband processing is implemented in a FPGA. The UWB link demonstration runs at 78.125Mpulse/s...
This study presents a new concept of implantable micro coil (1000 times 500 mum2) fabricated using an electroplating technique, used as receiver coil at 200 MHz for the measurement of small volumes and concentrations samples by NMR spectroscopy. Our goal is to determine its concentration sensitivity Sc and its limit of detection LOD. The MRI and simulation of RF field distribution allows defining...
This paper presents an experimental analysis of ReCoM, a novel reconfigurable architecture based on a mixed-grain reconfigurable array that combines a RISC microprocessor and a dynamically-configurable hardware for computation-intensive applications. The reconfigurable hardware is composed by mixed-grain reconfigurable cells that include 64-bits ALU, Look-Up Tables (LUTs), word-level arithmetic units...
Computer architects rely heavily on simulation to explore increasingly complex design spaces. Keeping simulations within tractable limits forces architects to evaluate only subsets of design parameters, which must be carefully chosen to yield accurate reflections of the benefits and costs of a new architecture. As a first step in formulating a methodology to appropriately evaluate processor design...
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