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The limits of the conventional chopper stabilization technique for cancelling the 1/f noise are studied theoretically and with simulations. The expected replicas of the 1/f noise at the chopping frequency and its multiples are attenuated by a modified chopping control. Simulation done using records of real 1/f noise outputs show that the spectrum of the signal does not change but 1/f replicas are...
A new parallel-in serial-out finite field multiplier using redundant representation for a class of fields is proposed. It has been shown that the proposed architecture has significantly lower complexity in comparison to the previously proposed architectures using the same representation. The new multiplier can be implemented in a hybrid fashion or at digit-level, which provides the designer with considerable...
In this paper, the performance of a Ring Laser Gyro based inertial navigation is studied. It is modeled by using two methods; in the dynamic modeling, some parameters such as scale factor and environmental sensitivity have been determined, whereas in the statistical model, the other parameters such as random drift have been computed. Also the performance of the system is evaluated for several inputs...
We describe in this paper two low power transmitters that operates within the 402-405 MHz band allocated for medical implant communication systems (MICS). A frequency modulation scheme is employed. Each one of the transmitters includes a frequency synthesizer, a power amplifier and a matching network. The difference between the two architectures relies on the frequency synthesizer, which uses a new...
In this paper, we propose two contributions to the simulation and design of an All-Digital Phase-Locked Loop (ADPLL) for RF applications. First, we extend the behavioral model we already proposed, in order to include detailed fractional aspects. Second, we propose a new adaptive algorithm that can be integrated in this ADPLL in order to lower its hardware complexity, and argue on a recently proposed...
This work reports a new implementation of a transistor model aiming to facilitate a closer understanding of nonlinear elements in silicon CMOS transistors operating at high frequencies. Using this model, the contribution of each non linear element to the total distortion of the transistor can be individually quantified using a superposition method. The new model is implemented entirely using symbolically...
Speech enhancement techniques, using spectral subtraction, have the drawback of generating an annoying residual noise with musical character. In this paper, we use and compare different post-processing methods of musical tones reduction. All these approaches need both a musical noise detector and a musical noise reducer. For each part, we propose 'non perceptual' and perceptual based approaches. The...
In this paper, we propose a time consistent video segmentation algorithm designed for real-time implementation. Our segmentation algorithm is based on a region merging process that combines both spatial and motion information. The spatial segmentation takes benefit of an adaptive decision rule and a specific order of merging. Our method has proven to be efficient for the segmentation of natural images...
Practical digital multimedia is usually encountered in compressed format, and as such it is highly desirable to develop watermarking algorithms that operate totally in the compressed domain. In addition, watermarking schemes working jointly with SNR-scalable compression algorithms would be of great interest since the watermarks could be entirely retrieved at a given bit-rate. In this context, this...
A study for the adjacent channel power ratio (ACPR) for modified linear amplification using nonlinear component (LINC) power amplifiers used in wireless communication systems when branch signals are digitally baseband filtered is proposed. The LINC is modified by sending the filtered branch signals and then combine them at the receiver. The IEEE802.11g standard, which operates at 2.4 GHz, employing...
A split delta-sigma ADC topology is proposed, which provides enhanced noise shaping by cross-coupling the quantization errors of the two halves of the structure. Unlike the multi-stage noise shaping (MASH) architecture, the new structure is insensitive to mismatch errors, and it does not reduce the stability of the loops. Simulations confirm the effectiveness of the proposed scheme.
The following topics are dealt with: analog modeling; biomedical circuits; biomedical systems; RF LNA; analog filters; DSP; data converters; digital architectures; FPGA; RF oscillators; voltage reference; signal processing; sensors; test IC; RF power amplifiers; image processing; RF passive components; high level circuits; multipliers; adders; dividers; decoding algorithm; image coding; analog telecom;...
This paper describes a cost effective artificial neural network implementation on an FPGA in three easy steps. Furthermore, it proposes the manner in which network layers are mapped into a particular hardware structure such that the performance and efficiency, with which the hardware resources are used, are greatly improved. A reconfigurable, parameterised neural node is presented as the basic building...
This paper presents a comparison between BiCMOS and CMOS op-amps to be employed in pipelined analog-to-digital converters. Single and two-stage architectures were considered; in addition, a couple of op-amps exploiting bipolar devices in the input stage are proposed. The amplifiers were designed for the first stage of a 12-b high-speed converter; op-amps are constrained by a fixed power budget and...
This paper presents a strategy for the optimal implementation of algorithms on reconfigurable system based on FPGA technology. The advantage and the originality of our approach are that the implementation obtained combines the execution of algorithm in dynamic reconfiguration realized by temporal hardware partitioning and/or architectural synthesis based on the re-using of the operators. Our approach...
In this paper, a systolic inversion architecture is proposed based on an optimized version of the Modified Extended Euclidean Algorithm (OMEEA). The proposed OMEEA employs signal reusability and simplification of the algorithmic control logic to achieve a less complex, hardware oriented version of Modified Extended Euclidean Algorithm. The resulting proposed systolic inversion architecture highlights...
We investigated the dynamic nature of a highspeed CMOS comparator, and present a comparator frequency-response model based on small-signal linear analysis of a latch. The analytical frequency model offers good insight into the linearity of the quantizer utilized in CTDeltaSigma modulators. In addition, a novel design guideline for a high-speed CMOS comparator to ensure the quantizer linearity is presented.
A new method is presented for the reduction of DC biasing power in nonlinear analog circuits. The key concept in this methodology is to remove the general biasing and replace it with "local biasing" of the individual devices in the circuit. The procedure limits the DC power consumption only to nonlinear devices for biasing purposes. The procedure makes these devices to respond to AC signals...
This paper deals with the problem of static error mismatch in time-interleaved analog to digital converter (TIADC). These deterministic errors between channels degrade the performances of the whole system. Software mathematical method is presented for offset and gain compensation of two TIADCs. Numerical simulation results are exposed to validate the theory and the proposed model.
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