The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A new single ended sense-amplifier based flip-flop is proposed whose the sense amplifier stage is modified such that a balanced rise/fall delay is achieved. The new flip-flop has a comparable timing characteristic of a Master-Slave latch with 25% power reduction. The proposed flip flop has the same transistor count as the peer Master-Slave flop which is widely used in current standard cell libraries...
In this paper, a robust, low-complexity timing synchronization algorithm suitable for 5.9 GHz advanced dedicated short range communications (ADSRC) system and its efficient hardware implementation is proposed. Cross-correlation technique is used to detect the starting point of short training symbol and the guard interval of the long training symbol. The design is implemented in a Xilinx Vertex-II...
Gaussian mixture models (GMM)-based classifiers have shown increased attention in many pattern recognition applications. Improved performances have been demonstrated in many applications but using such classifiers can require large storage and complex processing units due to exponential calculations and large number of coefficients involved. This poses a serious problem for portable real-time pattern...
In this paper, a low voltage current conveyor (CCII) based multifunction filter is presented. Firstly, thanks to an optimizing heuristic, an optimal sizing of a low voltage low power CMOS current conveyor (CCII) was done. Hence, we improve static and dynamic performances of this configuration. The optimized CCII configuration has a current bandwidth of 1.103 GHz and a voltage bandwidth of 1.18 GHz...
We make use of a discrete-time approach for the analysis of the steady-state and local stability of nonlinear circuits to compute the bifurcation boundaries of periodically forced nonlinear circuits. A bifurcation point may be detected by following a limit cycle solution as a function of a parameter until an eigenvalue crosses the unit circle. However, efficiency is improved by adding an extra equation...
This paper analyses power-supply noise induced timing variations in NAND and NOR logical blocks. The focus of this work is on the NAND and NOR blocks used in nonover-lapping clock generation circuits used for switched capacitor sigma-delta analog-to-digital converters. Monte-Carlo simulations performed in Spectre at BSIM3v3 transistor model level using parameters from two manufacturing processes,...
Monolithic active pixel sensors (MAPS) using standard low cost CMOS technology available from industrial manufacturers have demonstrated excellent tracking performances for minimum ionizing particles. The need for highly granular, fast, thin and radiation tolerant pixel arrays equipping vertex detectors drives an intense R&D effort, aiming to optimize the intrinsic sensor performances. Following...
This paper describes a wide frequency range and low jitter delay-locked loop. A new architecture is proposed for lock-detect circuit that solves the problem of false locking associated with conventional DLLs. The exact 50% duty cycle is not necessary for the correct operation of this architecture. The circuit design and ADS simulation are based upon TSMC 0.18mum CMOS process. The simulation results...
This paper presents a switch bootstrapping technique for very high sampling frequencies. The circuit has been implemented in a switched capacitor delta sigma A/D converter operating at 400 MHz in a 0.18 μm CMOS technology. The high sampling frequency allows to use a high oversampling ratio, resulting in a SNR of 53 dB and signal bandwidth of 3.125 MHz with a simple singleloop second order topology...
In this paper, a hybrid method for cereal grain identification is presented. This method combines a statistical pattern recognition method using morphological and color features and a new method based on the fuzzy logic decision making. The classification is made by the combination of these two methods. We achieved this method to win in precision of the statistical method and in capability of decision...
In most of bioimplantable or wireless sensor network systems, ASK is one of the most commonly used schemes to modulate the baseband signal with reference to the intermediate or even the carrier frequency. In this study, a novel demodulator architecture is proposed. It is based on a simple self-sampling scheme which is a truly low-cost high-efficiency implementation and has excellent ability to work...
This article introduces a frequency-controlled transcutaneous energy transfer system as well as a particular circuit structure for it. The analysis method, design and realization of this system are studied and its performance evaluation based on the simulations and experimental results of a prototype circuit is carried out. The simplicity of the required hardware as well as the high performance and...
In this paper we show how TACT, a recently reported radio system design and optimization tool, can be used to optimize the design of a dual mode WCDMA/WLAN receiver. An overview of the underlying frequency planning and receiver budget analysis routines is discussed first. In a case study, a zero-IF WLAN/WCDMA radio receiver is then designed and optimized using the tool. TACT yields optimized design...
This paper proposes an 11 Gb/s CMOS demultiplexer (DEMUX) using a redundant multi-valued logic (RMVL). Owing to the redundant multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than a conventional binary logic. The implemented DEMUX consists of eight integrators and each integrator is composed of an accumulator, a window comparator, a decoder and a D flip...
Direct sequence spread spectrum (DSSS) technique has been widely used in both military communications and commercial communications. The normal jamming types, including broadband noise, partial-band noise and so on, are ineffective at the current jamming power level when the processing gain is large enough. This paper proposes a design of the repeater jamming based on radio frequency memory (RFM)...
This paper presents a novel FPGA-based stereo matching system. The proposed circuit operates on 512times512 stereo images with a maximum disparity of 255. It achieves a 286 MHz running frequency and a frame rate of 25.6 f/s.
This paper proposes a novel architecture to realise a highly-efficient and linear bandpass (BP) delta-sigma (DeltaSigma) transmitter. The novel transmitter topology takes advantage of the fact that nowadays digital signals are in-phase (/) and quadrature (Q) modulated. Instead of using the combined signal, the proposed architecture processes the RF I and Q signals in two separate branches and combines...
In the present paper, a novel fully digital frequency shift keying demodulation architecture is examined. Unlike traditional designs, that use phase locked loops (PLL) to track the phase of the signal, the presented demodulator rely on linear feedback shift registers (LFSR) and Galois field arithmetic to directly compute the phase or frequency value. We are aimed at the highest throughput, even at...
Ultra-small radio frequency identification (RFID) chip with its antenna technology is described. The key techniques used in this ultra-small chip to reduce chip size and cost are embedded antenna, double-surface electrode and silicon on insulator (SOI).
This paper presents a new design methodology for optimum sizing and compensation of two-stage amplifiers based on a time-domain approach. This methodology allows the analysis of different topologies of amplifiers with an unlimited number of poles and zeros. The optimization process is performed by a software tool based on a genetic algorithm kernel integrated with open-source BSIM3v3 code. Using this...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.