The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Method of quasilinear approximation is applied to evaluate stability of operation of two coupled and synchronized van der Pol oscillators. Using this method, at the first step one obtains the amplitude transient equations (van der Pol equations). Then, using routine linearization of these equations one finds the system of four first order linear differential equations. Calculation of the roots of...
This paper presents LPRT, a new medium access control (MAC) protocol for wireless sensing and actuation systems. Some of the characteristics of the proposed protocol are low power consumption, support for real-time and loss intolerant traffic through contention-free operation and a retransmission scheme, flexibility, and high throughput efficiency. The LPRT protocol was implemented it in the MICAz...
We present an IP-core called PHCA for programmable hardware cellular automaton (CA). PHCA is a hardware implementation of a general purpose cellular automaton entirely programmable. The heart of this structure is a PE array with reconfigurable side links allowing to implement a 2-D CA or a 1-D CA. As an illustration of a PHCA program we present the implementation of a symmetric cryptography algorithm...
In this paper we propose an efficient low-hardware complexity post-processing module for a feedback-corrected chaos-based True Random Bit Generator (TRBG) with high Average Shannon Entropy (ASE). The design of the postprocessing module was based both on the theoretical analysis of the information generation mechanism of the considered source and on numerical simulations. A prototype of the module...
This paper presents an optimized design of an AIS/DSC homodyne receiver for maritime applications. Several receiver architectures are investigated and the optimal one in terms of noise figure and complexity is selected. AIS/DSC receiver is designed based on commercially available parts. The receiver's performance is found to meet the specifications through ADS simulations using commercial parts' properties...
One of the most challenging problems of clustering is detecting the exact number of clusters in a dataset. Most of the previous methods, presented to solve this problem, estimate the number of clusters with model based algorithms, which are not able to detect all types of clusters and also face a problem in detecting coupled clusters in a dataset. In this paper we propose a new method for finding...
A complete 2.4 GHz ultra low-power RF transceiver for IEEE 802.15.4 standard (ZigBee) applications is reported. The circuits have been designed by using a low-cost 0.35 mum BiCMOS standard technology. The receiver, which consists of a LNA and I/Q mixers, exhibits a noise figure of 8.7 dB, a voltage gain of 26 dB, an input-referred third-order intercept point of -13 dBm and a power consumption of 8...
A strategy to design high-speed low-power MOS current-mode logic (MCML) static frequency dividers is here proposed. Analytical criteria to exploit the speed potential of MCML gates are first introduced. Then, analytical criteria are formulated to progressively reduce the bias currents through the stages without affecting the divider operation speed, reducing the overall power consumption. The analytical...
Energy efficient LSI is becoming increasingly crucial for battery operated embedded portable applications. To reduce energy per transition and to improve performance for ultra-low voltage circuits, we proposed internal variable forward body bias technique for precharge-evaluate based logic circuits. In the proposed scheme, the forward body bias is applied to high threshold voltage of either the pull-up...
A novel integrated photonic architecture is introduced and used to realize an optical filter with direct form I realization. The architecture offers gain from semiconductor optical amplifiers, and this gain results in an active optical filter whose filter response depends on the individual gains. The presence of gain provides advantages in filter performance, and tunable and adaptive functionality...
A 4-Gb/s, low-power, 231-1 output length, pseudo random binary sequence (PRBS) generator with a wave-pipeline technique is presented. A thirty-one stages linear feedback shift register (LFSR), whose feedback taps are connected to the first stage through EXOR, is adopted. In this LFSR, each stage consists of D-FF employing a true single phase clock (TSPC) type to increase the operating frequency. In...
Two 32times6-bit read only memory (ROM) circuits, employing an architecture suitable for use as a phase to amplitude converter for direct digital synthesizers (DDS), have been designed in InP double heterojunction bipolar transistor (DHBT) technology. These ROM designs use a -3.8 V power supply and dissipate 1.95 W and 7.07 W of power respectively. The maximum operating clock frequencies for these...
In this work, we implement a MMSE RAKE receiver for ultra-wideband (UWB) system in a presence of a reach multipath environment, using an enhanced time-hopping system simulator. It is known that MMSE receiver has the best performance in terms of signal-to-noise-plus-interference-ratio (SINR) at the expense of high computational complexity. In addition, in order to process ultra-wideband signals, an...
In this work, the authors present a fully integrated, fully differential amplifier operating at 79 GHz using a highspeed Si/SiGe hetero-bipolar technology. This amplifier needs a single supply voltage and shows high performance such as high gain, excellent reverse isolation and low power consumption (90 mW at 3 V supply voltage). This result was achieved by using multi-stage cascode topology and a...
A 3 bits - 0.25 μm BiCMOS SiGe:C accumulator operating up to 15 GHz clock frequency is presented. It is based on a high-speed and low-power three-levels BiCMOS logic which is used to implement the 1 bit full-adder and the D-flip-flop latch-up register. With this technique, the dissipated power is reduced by 30% over the usual four-levels series logic. The circuit integrates 203 (without buffers, 230...
This paper presents a new architecture of an RF digital predistorter for power amplifier used in third generation base stations. Linearization of power amplifiers has been treated with many analogue design techniques in order to increase their bandwidth and their efficiency. The novelty is that this architecture is fully reconfigurable and acts on RF signals rather than BaseBand signals. The resulting...
This paper proposes an automatic redundant contact insertion method under timing constraints for standard cell yield enhancement. Contact failure is one of the most dominant yield loss reasons and redundant contact insertion is highly recommended to improve the yield. The proposed method inserts the redundant contacts as many as possible under given timing constraints using a linear Programming. The...
This paper propose a novel approach for modeling the end-to-end time delay dynamics of the Internet using system identification, and use it for controlling real-time Internet-based telerobotic operations. When a single model is used, it needs to adapt to the operating conditions before an appropriate control mechanism can be applied. Slow adaptation may result in large transient errors. As an alternative,...
A charge pump topology with enhanced driving capability for very low voltage applications is presented. The proposed scheme is able to operate with a supply voltage as low as 900 mV and ensures high voltage gain, high driving capability, and high power efficiency over the whole current range. A suitable boosting circuit allows adequately low on-resistance of transfer devices while still limiting the...
In this paper, we propose a method for cryptanalysis of the Shi reversible data hiding algorithm. We also propose a method to improve its security by using the concepts in number theory. Our security improvement part encrypts the data by four keys before embedding it in the digital image and in the detection part the keys are used as side information to recover the original data. Theoretical analysis...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.