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Excessive power during test affects the reliability of digital integrated circuits, test throughput and manufacturing yield. Numerous low power test methods have been investigated over the past decade and new power-aware automatic test pattern generation, design-for-test and test planning techniques have emerged. This embedded tutorial introduces the topic of low power test and it overviews the basic...
Driven by the increasing complexity of integrated circuits, the pressure on test cost reduction increases exponentially as productivity on chip level progresses according to Moore's Law. A high-level strategic approach for test cost target setting and planning will be explained. The intention is to keep cost of test constant relative to overall cost of goods sold. This method has been developed and...
This tutorial discusses test methods and voltage stress approaches required to ensure effective cost effective defect screening to produce high quality, reliable products. Wafer level reliability screens (WLRS) refers to the application of screens during wafer test that will both activate and detect a sufficient number of defects so that early life failure rate (ELFR) is reduced enough to meet customer...
This talk will discuss the evolution of test and diagnosis, in the broad sense, over the recent years as well as the outlook into the future. Test, as it was only recently a pure discriminator between good and bad, has gained significant more added value by acting also a feedback loop towards the manufacturing process of integrated circuits. Of course, this feedback loop was already there, but was...
This paper proposes a self-test method of dynamically reconfigurable processors (DRPs) without area overhead. This method constructs a test frame of processor elements (PEs) such that it consists of test pattern generators, response analyzers and PEs under test, and switches several test frames dynamically so as to test all the PEs. Since the number of contexts and test application time are subject...
Summary form only given. Do you know how many ENIAC vacuum tubes were replaced every day during its heyday? What did it teach us about Test, or design-for-test? did Eldred really invent the stuck-at fault model in 1959? Is 99.999% fault cover all it's cracked up to be or are we fooling ourselves? Are we better off with 115% or even 80%? Where did Design-For-Test come from? Where is it now? Where's...
Diagnosis is essential in modern chip production to increase yield, and debug constitutes a major part in the pre-silicon development process. For recent process technologies, defect mechanisms are increasingly complex, and continuous efforts are made to model these defects by using sophisticated fault models. Traditional static approaches for debug and diagnosis with a simplified fault model are...
RF test signals are a requirement for the implementation of effective BIST techniques in transceivers. In this work a method to encode a binary signal with the desired RF frequency is presented. The approach employs high-pass sigma delta modulators, in contrast to conventional low- pass or band-pass approaches, allowing signal generation close to the Nyquist limit of FS/2 (FS=sampling frequency)....
Standard automated test equipment (ATE) for radio frequency (RF) transceiver production testing of today is limited by digital signal processing and data transfer. These constraints can be considerably relaxed by the application of new technology based on field programmable gate array (FPGA). The methods proposed are capable of handling all tasks flexibly and at-speed. FPGA hardware resources are...
A novel statistical learning algorithm is proposed to accurately analyze volume diagnosis results. This algorithm effectively overcomes the inherent ambiguities in logic diagnosis, to produce accurate feature failure probabilities, which are critical in understanding systematic yield limiters. The results of Monte-Carlo simulation are presented, which demonstrate the feasibility and impacts of various...
We describe a diagnostic test generation procedure that deals with the large numbers of target fault pairs by considering subsets of faults. Each subset of faults is targeted separately during diagnostic test generation, and fault pairs are defined only out of the faults included in a subset. With M subsets of size K, the number of fault pairs considered is at most MK(K-1)/2 instead of N(N-1)/2 for...
An efficient method of parallel fault simulation for combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks of gates. Converting gate-level circuits to the macro-level is accompanied with fault collapsing. A parallel fault analysis algorithm for SSBDDs was developed...
Software-based self-test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the most popular applications falling in this category are the various mobile devices. However, in-field testing of processors integrated in mobile devices has the extra requirement of minimum energy consumption, since these devices...
This paper presents a technique that enables online testing of sensors through the superposition of the test stimulus onto the measurand. Perturbations due to the surrounding environment can very often introduce fluctuations in the test output that is a major concern for this type of sensor testing. This paper proposes a novel approach to tackle this problem by encoding the test stimulus using a pseudo-random...
An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Therefore embedded memories are commonly equipped with spare rows and columns (2D redundancy). To avoid the storage of large failure bitmaps needed by classical algorithms for offline repair analysis, existing heuristics for built-in repair analysis (BIRA) either follow very simple...
In this paper, we present an analysis of resistive-open defects in the sense amplifier of SRAMs designed with the Infineon 65 nm technology. From manufacturing data, we show that in some cases, a resistive-open defect may lead to a new type of dynamic behavior which has never been published in the past. This faulty behavior can be modeled as a dynamic two-cell Incorrect Read Fault (d2cIRF). Such d2cIRF...
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