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High writing current is the bottle-neck of PCM application and efforts focus on merely materials doping to improve crystal resistivity, novel structure to decrease active area etc. Here some solutions of our group are shown, including Si doped GST, novel 2D and 3D memory cell structure and multistate storage
This paper introduces several advanced tunnel dielectrics, synthesized by the MAD technique, to overcome the scaling limitations encountered by the current flash memory technology. Because of space limitations, only trap-less silicon nitride will be covered in this write-up
For the purpose to detect the low capacitance signal, which emerged in noise, the virtual instrument based detection scheme was used in the novel prototype of micro gyroscope structure. Software arithmetic and the software generated reference waveform were designed for the demodulator to pick up the variable capacitance. The result of the experiment shows that the software realized demodulator can...
To enhance the measurement range of capacitive micromachined accelerometer, a nonlinear model in open loop mode is proposed. It is pointed out that in the relation curve between input acceleration and output voltage; there is maximum measurand acceleration amax which is decided by both the original distance d between electrodes and the ratio lambda of spring constant to mass. The accelerometer can't...
Aluminum nitride (AlN) thin film bulk acoustic resonator was fabricated using silicon bulk micromachining technique with highly c-axis oriented piezoelectric cell. AlN piezoelectric films were deposited on both platinum (Pt) and gold (Au) bottom electrodes under optimized sputtering condition for comparison. The measurement results of X-ray diffraction, scanning electron microscope, and atomic force...
In this paper, the authors demonstrate the improvement of HfSiON pFET characteristics with F incorporation technique, which might be a powerful tool to lower Vth in pFET with both poly-Si and PC-FUSI gate. Using F implantation in channel region prior to HfSiON formation Vth lowering up to ~200mV is obtained without mobility degradation. Furthermore, impact of F incorporation in HfSiON is investigated...
Germanium MOS capacitors with high-quality gate dielectrics are fabricated by novel processing in wet ambients. Wet NO oxidation with wet N2 annealing is used to grow GeON gate dielectric on Ge substrate. As compared to dry NO oxidation, negligible growth of unstable GeOx interlayer and thus a near-perfect GeON dielectric can be obtained. This idea is extended to high-k gate dielectric (HfTiON), which...
In this work, it was demonstrated that the Fermi level pinning in poly-Si/HfO2 can be effectively suppressed by using poly-SiGe gate. Threshold voltage of -1.02 V in poly-Si/HfO2 PFET was tuned to -0.81 V in poly-Si/Al2O3/HfO2, and further reduced to -0.49 V in poly-Si/poly-SiGe/Al2O3/HfO2. At the same time, Vth of 0.3 V for NFET was achieved in this poly-SiGe gate stack. Moreover, Vth stability was...
A mobility model is developed for strained-Si N-MOSFETs accounting for the various mechanisms such as surface roughness scattering, optical phonon scattering and coulomb scattering that cause degradation in effective carrier mobility. The proposed semi-empirical model is in good agreement with experimental data for a wide range of temperatures, doping densities and Ge mole-fractions
Effect of surface roughness on quasi-ballistic transport in nano-scale Ge and Si double-gate (DG) MOSFETs are investigated using 2D full-band self-consistent ensemble Monte Carlo (MC) method based on solving quantum Boltzmann equation (QBE). Results show that the effect of the surface roughness on carrier quasi-ballistic transport in DG nMOSFETs is still significant even when the gate length scales...
Spectroscopic ellipsometry (SE) has been extended to the non-destructive, in-line monitoring of biaxial tensile strain in strained silicon (epsiv-Si). SE data from 250nm - 500nm from three epsiv-Si samples were fitted using a new parametric model for semiconductors. By using the E1 peak shift in the fitted dielectric function spectra, the tensile strain in epsiv-Si can be monitored. Strain values...
Uniaxial strain relaxation of ultra-thin biaxial-tensile SSDOI is realized by ion-implant amorphization and solid phase epitaxy (II/SPE). The selective full amorphization in the thin SSDOI region, between raised source/drain (RSD) and channel, induces uniaxial strain relaxation in the channel. The SSDOI uniaxial strain relaxation enhances PFETs drive current by more than 20%
This work reviews the current progress in high-mobility strained MOSFETs and covers the latest developments in strain engineering. The paper focuses on the connections between strain, band structure, and channel mobility characteristics. The authors show that accurate band structure calculations are essential to understand the different mechanisms of mobility gain induced by uniaxial and biaxial strain...
This presentation summarizes some of the most recent Si innovations made for advanced CMOS transistors in the nanotechnology era. Through these Si nanotechnologies, it is expected that CMOS scaling and performance trends extend and continue well into the next decade. Additionally, there has been much interest generated recently in the research of non-silicon materials and nanoelectronic devices and...
The paper discusses the mission and findings of our MARCO Focus Center on Functional Engineered Nano Architectonics (FENA) and the Western Institute of Nanoelectronics (WIN). In the Center and the Institute funded by SIA, we explore different logic state variables, such as the use of particle spin, molecular conformation and others in addition to today's charge based electronics, for resolving the...
Interconnect effects have become a more and more important factor in high performance chip design. In traditional floorplanners, the lack of information about high level synthesis (HLS) timing based on cycle paths often leads to frequency violation in flooplan. In this paper, timing analysis including interconnect delay and chip frequency optimization are introduced to floorplanning, which brings...
A novel control technique optimized for digital power factor correction (DPFC), which consists of two loops: "outer voltage loop" and "inner current loop", is presented. The current loop employs predictive dead beat (PDB) technique to boost the switching frequency. The voltage loop employs "voltage sensor-less technique", which senses in an interleaving manner the inductor...
For large layout SOC design, one centralized controller easily brings on so long control wires that system cycle doesn't satisfy timing constraint. This paper proposes a self-adapting multi-kernel controllers generating and placing method. According to different timing constraint, it partitions the control points into different number groups, then generates a local controller for each group and places...
In this paper, we introduce various candidates for circuit blocks so that the floorplanner can dynamically choose the implementations of blocks to optimize the whole chip. Especially in 3D IC design, some components may occupy more than one layer, we propose a novel method to optimize the cubic packing with various candidates. Based on 3D-CBL (3-dimensional corner block list) representation, we can...
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