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In this paper, a double capacitive body biased keeper (DCBBK) for domino logic gate is proposed. By using this technique, the threshold voltage of keeper transistor adapts to multi operating phase to reduce leakage power consumption and enhance speed compare to other techniques such as standard domino (SD) without body bias, dynamic body biased keeper (DBBK) and single capacitive body biased keeper...
A new conception called performance-vector is proposed in this paper to measure the performance of prefix adders. According to the theory, a kind of high performance low-power prefix adder with sparse-tree architecture is introduced. The proposed adder is implemented using both static CMOS and semi-dynamic logic. The simulation result shows that this design has higher speed, lower power and smaller...
The purpose of this work is to explore the optimum LNA design that input impedance match, gain, noise figure, linearity, and power consumption, in this LNA design operating at the 10GHz has been simulated based on a TSMC 0.18-mum RF CMOS process. This paper presents a 10 GHz operation is designed and implemented in a standard cascode LNA technology for an 802.16a application. The LNA exhibits a noise...
In this paper, a variable band structure which can be used for wireless front-end circuits is proposed. Based on this structure, a single-ended one-stage cascode low noise amplifier (LNA) is presented for future multi-band and multi-standard wireless applications. A band selective performance is achieved by utilizing a varactor at the output matching circuit. The LNA implemented in 0.25 mum BiCMOS...
A direct up-conversion mixer from 1MHz to 2.4GHz implemented by TSMC 0.18mum 1P6M CMOS process is demonstrated. In this design, the combination of the concepts of "active dual-gate mixer" and "passive FET mixer" is used to achieve mixing effect. With the "folded" structure, this mixer can operate at low voltage (1V) normally. As the results show, the conversion gain is...
A model is proposed to account for the high-frequency characteristics of double-gate (DG) MOSFETs. Parasitic gate capacitances and gate resistances, associated with the geometry of DG MOSFETs, are investigated in detail. The model is verified by physical device simulation. Furthermore, the behavior of devices in the RF domain, including frequency responses and high-frequency noise performance, are...
Mobility bias-dependence is usually modeled by the effective electric field (Eeff). However, the influence of different device structures and quantum effect on the Eeff has not been thoroughly studied. In this paper, the Eeff in ultra-thin body (UTB) and double-gate (DG) MOSFETs is derived from the Poisson equation. Based on the Eeff, symmetric DG devices show higher mobility than asymmetric DG and...
The mobility degradation in ultrathin-body (UTB) SOI MOSFETs with high-k gate stack induced by Coulomb scattering rates is studied. The Coulomb scattering limited electron mobility for different gate dielectric materials and different silicon body thickness are calculated based on Coulomb scattering theories. The results show that increasing the dielectric constant of high-k gate dielectrics and decreasing...
A novel partially-depleted (PD) silicon-on-insulator (SOI) MOSFET with a T-shaped body (TSB) is proposed for the first time. Simulation results demonstrate that the proposed structure provides nano-scaled PD SOI devices with much better short channel effect immunity and sub-threshold characteristics than those of UTB SOI devices. It is also shown that the threshold voltage of proposed device can be...
A novel polysilicon gate quantum effect model for MOSFET devices is presented. Only two fitting parameters are required to account for the polysilicon gate quantum effects. It is shown that neglecting the polysilicon gate quantum effects for nanoscale MOSFETs may lead to a lager error in gate capacitance. Comparing with the Medici simulated results validates the model
In this paper, the gate-electrode fringing capacitance of nano-MOSFET is derived by conformal mapping transformation. Threshold voltage including the fringing-capacitance effect is calculated and good agreement with experimental data is obtained. Factors impacting the threshold behaviors of nano-MOSFET are discussed in detail
We summarize our recent results for the induced exchange interaction due to thermal bosonic environment (bath) which also generates quantum noise. Our focus here is on the onset of the interaction. We demonstrate that the induced interaction can be used to manipulate and create entanglement over time scales sufficiently large for controlling the two-qubit system for quantum computing applications,...
A new coarse tuning loop for wide-band dual-loop frequency synthesizer is presented in this paper. The proposed coarse tuning structure is composed of successive approximation register (SAR) and new structure frequency comparator. The frequency comparison error is analyzed and shows less comparison error compared with reported ones. This structure also reuses the programmable divider as a part of...
In this paper we present a design of adaptive gain phase-locked loop (PLL) which features fast acquisition, low jitter and wide tuning range. A dual-edge-triggered phase frequency detector (PFD) and a self-regulated voltage controlled oscillator (VCO) are employed in this design to realize the aforementioned properties. The measured results show that the experimental chip with a standard logic 0.5-mum...
In this paper, the MCU core is partitioned into data path units and control units. Since the data path is one of the key factors that influence the performance of MCU, much effort has invested to its design. A data path model is elaborately designed. ALU is optimized using operand isolation for power reduction. Four-level read scheme is adopted for general purpose registers design in order to reduce...
Hardware/software (hw/sw) partitioning is a critical step in the co-design, it directly affects the system performance largely. Targeting the shortcomings existed in the traditional algorithms, in this paper a guiding function based greedy partitioning algorithm (GFBGPA) is presented. The algorithm especially aims at the parameterized FPGA coprocessors architecture. The guiding function is determined...
Finite fields have been used for numerous applications including error-control coding and cryptography. This paper presents a high-speed area-efficient architecture for arithmetic that can support arbitrary irreducible polynomials in GF(2m). The arithmetic unit can perform the Galois field arithmetic operations of addition, subtraction, multiplication, squaring, inversion and division. The least significant...
In this paper an overview of diamond technology and its future prospects are presented. Technological problems facing the technology and how it can be addressed will be discussed
The GaAs-based MOS-HEMT with oxide as the gate dielectric and HBTs with surface passivation prepared by liquid phase oxidation has been successfully demonstrated. As compared to its counterpart HEMTs, the larger gate swing voltages, lower gate leakage currents, and higher breakdown voltages make the proposed technique suitable for power device applications. Moreover, the HBTs with oxide passivation...
A 2-Kbit low-power embedded EEPROM memory, which is based on SMIC 0.35 mum three-metal two-poly mixed signal CMOS technology with embedded EEPROM technology, has been developed. Key design techniques of power dissipation optimization for EEPROM memory are described. Optimizations of the current consumption for the charge pump circuit are treated in this paper. To optimize the read access power consumption,...
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