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Strain relaxation process of SiGe-on-insulator (SGOI) structures in the oxidation induced Ge condensation method was investigated as a function of SiGe thickness. Complete relaxation was obtained for SiGe layer having the thickness of more than 60 nm, leading to the establishment of highly relaxed SGOI wafer fabrication. The photoluminescence evaluation of the strained Si/SGOI wafers showed high Ge...
The optimization of digital circuit test set can reduce VLSI test cost by compacting test vectors and cutting down test time. Ant colony optimization (ACO) and particle swarm optimization (PSO) are the novel bionics optimization algorithms on the basis of iteration. Utilizing intelligent hybrid optimization algorithm of ACO and PSO can delete redundancy of test vectors so as to solve the optimization...
This paper presents a new BIST reseeding method that can significantly increase the ratio of test data compression using one LFSR seed to encode multiple deterministic test patterns. Experimental results on ISCAS89 benchmark circuits show that this method has about 30% reduction of the seed number
There have been some researches of testing CLBs in SRAM-based FPGA in recently years. While no research in existing papers has focused on testing and locating multiple stuck-at faults in CLBs. We propose a testing approach for this multiple faults model and try to reduce the number of test configurations (TCs) and test vectors (TVs). It is certificated that in the proposed testing, the number of TCs...
This paper presents a DFT (design for test) solution which combines boundary-scan and full-scan together in SoC testability design. Using this method, full scan test and boundary scan test can be easily performed just through the common IEEE 1149.1 (JTAG) access interface. Our final goal is not only to implement fewer test-pin-count, but rather to provide an IEEE 1149.1 compatible architecture to...
This paper proposed a novel low leakage FPGAs look-up table (LUT) that can operate in three different modes: high-speed, low-power or sleep. In high-speed mode, the LUT provide similar power and performance to a conventional LUT. In low-power mode, as the expense of speed, leakage power is reduced by 68%~73% vs. high-speed mode. Leakage power in sleep mode is over 95% lower than in high-speed mode
Previous researches on switch blocks focused on the analysis of individual switch blocks that contain single length segments. In those switch blocks, segments of different length are separated from each other, which results in low efficiency and low speed. This paper presents a methodology to realize the switching between segments of different length. This methodology considers the design of switch...
Image scaling plays an important role in digital image processing. It is widely applied in all sorts of display terminals. A new scaling method was proposed in this paper. The method combines traditional nearest neighbor and bilinear methods in a simple but effective way. The hybrid algorithm was discussed based on analysis of its idea origin. Multiple input interpolation method was put forward for...
This paper presents a novel 128-point FFT processor developed primarily for the application in a MB-OFDM based UWB system, in which a N=4*4*4*2 algorithm was exploited. A radix-22 unit and a radix-22/2 unit form the two-stage pipelined architecture. The parallel butterfly unit enhances the processing speed efficiently. Moreover, a unique butterfly both shared by radix-22 and radix-2 is proposed to...
A double-edge-triggered phase frequency detector (dec-PFD) with modified true single phase clock D flop-flip (TSPC-DFF) is presented in a 0.35-mum CMOS technology. Due to a dead zone of 15 ps and three-state property, the dec-PFD can work up 1.5 GHz with decreased phase errors and jitter. The power consumed at 100 MHz is 0.74-mW from a 3.3-V power supply. The maximum frequency, phase characteristics...
The increasing system resources available on field-programmable gate arrays (FPGA) enable the integration of complex system on one programmable chip. This paper focuses on the design and implementation of a hierarchy-bus based multi-processor system-on-chip (MPSoC) integrating 4 ARM processors on FPGA. Experimental results had been obtained running at 60MHz with total area requiring 34% adaptive look-up...
Power is becoming a crucial design constraint for nanometer FPGAs. In this paper, we investigate the FPGA routing architectures on determining the best distribution of routing segment length considering energy, performance and area tradeoffs. We present evaluations on two new Vdd-programmable architectures and found that the best FPGA architecture uses Vdd-programmable clusters and Vdd-gateable interconnects...
The most charming feature of FPGA is that it is post-fabricated, which means that user can design his own logic onto the chip without the need of tape out. So both design cycle and prototype cost can be greatly reduced. Once the bit file - which is a binary file representing the user designed logic s generated, it should be downloaded into the chip to realize the user logic. This paper deals with...
Novel G4-FET based logic-circuits (adjustable-threshold inverter, real-time reconfigurable logic gates and DRAM cell) are experimentally demonstrated. The independent action of the four gates helps minimize the required transistor count per logic function while enhancing design flexibility
For 65nm and beyond process technologies, identical transistors within a die can show large variations in on-current characteristics for different layouts. The proximity to the transistor of edges associated with different mask levels contribute to variability. Lithography proximity effects are dominant but other physical phenomena encountered with various process steps such as ion scattering, transient...
New technologies are continually being developed that enable designers to create faster, more complex circuits, packed within a shrinking die. However, along with the promise of speed and density comes the challenge of variability, as intradie device mismatch looms proportionately greater. To deliver new products in a timely and cost effective manner, the designer must have the methods and tools to...
This paper discusses the technology platform development for IC design in nano-CMOS technologies. New effects and issues in nano-CMOS are reviewed before the discussion on the contents of the technology platform. Some key components are briefly discussed with the exploration of some further challenges to develop a RF SOC design technology platform. An advanced technology platform with strong links...
Two novel low power wide OR domino designs are presented in this paper. With the same delay time, the two designed dominos decrease the active power by 8.92% to 17.25% and 13.79% to 25.84% as compared to the standard dual Vt dominos in a 45nm CMOS technology. In the meantime, the total leakage current is reduced significantly at two typical die temperatures
A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30mum. The total layout area is 2mm2 in 0.18mum CMOS and the chip thickness is 10mum. 4-phase TDMA reduces crosstalk and the BER is <10-12. Bi-phase modulation is used to improve noise immunity, reducing...
Asynchronous circuit dramatically reduces power and electromagnetic emission with respect to synchronous case, and can be easily integrated in a system on a chip (SOC). De-synchronous circuit is a commonly used asynchronous circuit. A de-synchronous circuit design flow is described in this paper. The hybrid cell library, consisting of standard cells and custom cells, is used. The standard cells are...
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