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A Nyquist-rate time-interleaved current-steering digital-to-analog converter (DAC) with dynamic channel matching (DCM) is proposed. Thanks to the proposed Nyquist-rate time-interleaved architecture, the DAC can properly operate at more than 1GS/s for a near-Nyquist output signal. The key limitation of the time-interleaved architecture is the mismatches between channels. The proposed DCM method can...
This paper describes the first gigasample rate time-based Nyquist analog-to-digital converter (ADC), consisting of a voltage-to-time-converter (VTC) followed by a time-to-digital-converter (TDC). After tuning, the 3-bit 2.5GS/s ADC designed in 90nm CMOS is measured to have an effective number of bits (ENOB) greater than 2.1 up to the Nyquist frequency. The power consumption, not including the TDC...
An ultra-low-power area-efficient 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) is presented. To achieve ultra-low-power performance a DAC architecture is proposed that employs two rail-to-rail low-power unity-gain buffers and only 4 minimum-size capacitors instead of the conventional binary-weighted capacitor array. Thereby, power consumption and area are drastically...
A high speed pseudo differential three stage operational amplifier has been implemented using a feed-forward compensation technique in a standard 0.13 µm CMOS technology. The three stage inverter based op-amp with feed-forward compensation achieves 11 GHz of unity gain bandwidth for a nominal power consumption 18 mW, and exhibits 39 dB of DC gain with phase margin of 62° when driving a differential...
This paper presents a high-speed, low-power and wide signal swing differential dynamic amplifier using a common-mode voltage detection technique. The proposed dynamic amplifier achieves a 15.5 dB gain with less than 1 dB drop over a signal swing of 1.3 Vpp at an operating frequency of 1.5 GHz with a VDD of 1.2 V in 90 nm CMOS. The power consumption of the proposed circuit can be reduced linearly with...
The present paper addresses an improved and compact low-power high-speed buffer amplifier topology for large-size liquid crystal display drivers. The proposed buffer achieves fast driving performance, draws a low quiescent current and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing and settling capabilities by realizing a dual-path push-pull operation of the output...
This paper describes a high-voltage-enabling circuit technique for enhancing the gain precision and linearity of OpAmp-based analog circuits. Without resorting from specialized devices, a 2xVDD-enabled recycling folded cascode (RFC) OpAmp optimized in 1V GP 65-nm CMOS achieves, when compared with its 1xVDD counterpart, 25-dB higher open-loop DC gain and 30-dB higher IM3 (in closed loop), under a similar...
This paper presents a new low-voltage output capacitorless low dropout (LDO) voltage regulator for System-on-Chip (SoC) applications. A low-impedance loading network is introduced at the output of LDO to achieve full range stability from 0 to 100 mA load current at a 100 pF parasitic capacitance load. No minimum output load current is needed whereas the quiescent current is made low. Thus, it improves...
In an effort to build versatile automotive Micro Controller Units (MCU's), power management has been integrated into the last generation SoC, with the additional benefits of simplifying board design and lowering the cost of bill of materials. In this paper we present a novel architecture for a 5 V to 3.3 V linear voltage regulator which can operate in dual mode: regulator controller, when an external...
This paper presents an output-capacitor-free adaptively biased low-dropout regulator with sub-threshold undershoot-reduction (ABSTUR LDR) for SoC power management applications. Techniques of Q-reduction compensation and adaptive biasing (AB) are employed to achieve low-voltage high-precision regulation with enhanced loop bandwidth while maintaining low quiescent current and high current efficiency...
A low power, high speed (480Mbps) envelope detector for serial data systems such as USB2.0 is presented in this paper. The proposed architecture is based on a high frequency rectifier implementation along with a comparator and offers about 50% power and area saving compared to prior implementations using multiple comparators. A calibration scheme to make the envelope detector process, voltage and...
Design optimization methodology of an output capacitor-less low-dropout regulator with small internal compensation capacitance for on-chip application with slew-rate enhancement circuit is presented in this paper. The on-chip compensation capacitance is reduced down to 1.5pF. The idea has been modeled and fabricated in a standard 0.35µm CMOS process. From experimental results, with minimum dropout...
We present a 45nm half-differential 6T SRAM (HD-SRAM) with differential write and single-ended read, enabling asymmetric sizing and VTH selection. The HD-SRAM bitcell uses SRAM physical design rules to achieve the same area as a commercial differential 6T SRAM (D-SRAM). We record measurements from 80 32kb SRAM arrays. HD-SRAM is 18% lower energy and 14% lower leakage than D-SRAM. It has a 72mV-lower...
This paper introduces a Dynamic Read SRAM (DRSRAM) architecture for high-density subthreshold RAM applications. DRSRAM performs a dynamic read operation to overcome the poor stability and bitline leakage problem of 6T SRAM cell in sub-threshold region. It is shown that there is fundamental limit for wordline activation time and recovery time under a given cell mismatch and bitline leakage. To verify...
This paper presents a new technique to accurately measure the data retention voltage (DRV) of large SRAM arrays in the presence of process variations. The proposed technique relies on a built-in-self-test (BIST) unit along with a DC-DC converter. The BIST unit implements a modified version of the March C- test that accounts for data retention faults. Whereas, the DC-DC converter is used to scale down...
A low leakage memory is an indispensable part of any sensor application that spends significant time in standby (sleep) mode. Although using high Vth (HVT) devices is the most straightforward way to reduce leakage, it also limits operation speed during active mode. In this paper, a low leakage 10T SRAM cell, which compensates for operation speed using a readily available secondary supply, is proposed...
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