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This paper presents a battery-connected wireless ion sensing system comprising a Na+-selective electrode, a 406 pW Potentiometrie front end, a 780 pW reference-free asynchronous SAR ADC, a 2.4 GHz power oscillator-based transmitter that consumes 2.4 nW when transmitting 100 bps, a 485 pW quiescent power 1.8-to-0.6 V switched-capacitor DC-DC converter with 96.8% peak efficiency, and two temperature-stabilized...
A fully synthesizable analog-like loop filter for a Low-Dropout regulator using only digital standard cells is proposed. To accommodate this, various blocks such as comparator, time-to-digital converter and charge-pumps are developed using only standard cells. The fabricated prototype in 0.13μm process occupying 0.0875mm2 provides 15mA current with minimum quiescent current of 140μA and load transient...
Reference drivers for charge-redistribution SAR ADCs require significant area and/or power. In this work, a low-power and area-efficient passive reference-voltage driving scheme for charge-redistribution SAR ADCs is proposed. An on-chip decoupling capacitor is pre-charged to a reference voltage during tracking phase and utilized to drive the DAC passively during conversion. The reference-voltage drops...
This paper presents an integrated fully differential current driver for wearable multi-frequency electrical impedance tomography (EIT). The integrated circuit (IC) comprises a wideband current driver (up to 500 kHz) functioning as the master for current sourcing, and a differential voltage receiver with common-mode feedback configuration as the slave for current sinking. The IC is fabricated in a...
The 60 GHz frequency synthesizer presented here demonstrates a transmitter error vector magnitude (EVM) between −28.8 and −26.5 dB, from 54 to 64.8 GHz, in 28 nm digital CMOS technology. This is suitable for IEEE 802.11-2016 communications with coded datarates up to 6.4 Gb/s. Its architecture, based on subharmonic injection locking, is immune to pulling by the power amplifier. A 24 GHz phase-locked...
A new face detection SoC integrating CIS array with low-power face detector on a single chip in analog-digital mixed-mode is proposed for ultra-low-power mobile device applications such as always-on user authentication. The proposed event-driven mixed-mode face detection SoC performs Viola-Jones face detection with not only analog face detection circuits but also digital vision processor. The analog...
This paper introduces an accuracy/energy-flexible configurable 2D Gabor filter based on stochastic computation, where bit streams representing information are used. The Gabor filters show a powerful feature extraction capability, but the calculation based on binary computation is complicated. As opposed to traditional memory-based methods that use fixed Gabor coefficients calculated by software in...
Vision of patients with retinal implants is diminished by spatial lowpass behaviour of the interface between electrode and stimulated cells. Spatial highpass filtering can compensate the interface lowpass to a certain degree and thus improve visual perception. The retinal implant consists of an array of photodiodes, each with an amplification circuit and an electrode. The proposed spatial highpass...
A 300 MHz-12 GHz HBT-based mixer-first receiver in 130 nm BiCMOS is presented. The mixer core is composed of four SiGe HBTs driven by quadrature LO pulses with a shared emitter RF input and feedback from the baseband to HBT bases to generate baseband-to-RF impedance-transparency. This is analogous to effects seen in CMOS passive-mixer-first receivers, but at higher frequencies than attainable with...
We present a cross-correlator ASIC for synthetic aperture imaging of Earth's atmosphere. Reconfigurability as a 2-level 96-channel or 3-level 48-channel cross-correlator provides adaptability to a wider array of applications. Implemented in a 65-nm CMOS process, the cross-correlator is capable of running at clock speeds of up to 3 GHz. In 2-level 96-channel mode, the cross-correlator consumes only...
A compact differential voltage reference cell, which combines an original switched capacitor integrator with a digitally programmable bandgap core, is presented. The two-stage integrator maintains an always-valid output voltage while performing correlated double sampling to effectively reduce the effects of offset and flicker noise. Measurements performed on a prototype designed with the UMC 0.18...
The presented wide-Vin step-down converter introduces a parallel-resonant converter (PRC), comprising an integrated 5-bit capacitor array and a 300 nH resonant coil, placed in parallel to a conventional buck converter. Unlike conventional resonant concepts, the implemented soft-switching control eliminates input voltage dependent losses over a wide operating range. This ensures high efficiency across...
An efficient near-field RFID reader, delivering power to and receiving data from Brain-Machine Interface implants, is realized in 65 nm CMOS. A modified Class E/Fodd Power Amplifier with a current-sense resistor differentially drives a single segmented antenna, and acts simultaneously as TX and RX. It operates at 309 MHz and has 54% efficiency. The backscattered data is recovered from the current-sense...
This paper describes the design of a high-density 4,096-pixel electrochemical biosensor array in 180nm CMOS for biomedical applications that require multiple analyte detection from small (5μL) samples. Each pixel of the array contains an exposed 45×45μm2 interdigitated micro-electrode surrounded by a ∼9pL nanowell fabricated using only a standard CMOS process along with a simple electroless gold plating...
This paper presents a 2×14bit cartesian Direct Digital RF Modulator (DDRM) in 28nm CMOS. Both AM and PM calibration circuits are introduced to relax matching requirements of the DDRM units which results in a compact and efficient implementation. The DDRM features a memoryless current source based unit cell to avoid complex dynamic digital predistortion (DPD) algorithms. All the units can be tuned...
This paper presents a low voltage 5GHz WLAN receiver (RX) with 0.8V power supply. The RX targets 802.11ax standard implemented in CMOS technology node from 28nm to 14nm whose power supply voltage will decrease to 0.8V. The RX presents three key techniques that overcome the challenges for the low voltage operation. An RF amplifier employs a variable source degeneration to improve the linearity. A quadrature...
Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to traditional SRAM, due to its high-density, low-leakage, and inherent 2-ported operation, yet, its dynamic nature leads to limited retention time that requires periodic, power-hungry refresh cycles. This drawback is further aggravated in scaled technologies, where increased leakage currents and decreased in-cell storage capacitances...
Content addressable memory (CAM) performs parallel data search at the cost of high area and power penalty. We propose a high-speed 6T-ReCSAM (Reconfigurable CAM/SRAM) with new energy efficient sensing technique. Proposed implementation is compatible with compact 6T-SRAM foundry bitcells. Test-macro of 8Kb is implemented in 28nm FDSOI CMOS and reaches up to 1.56GHz at 0.9V with 0.13fJ/bit energy consumption...
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