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In this paper, a 10b 100-to-500 kS/s asynchronous SAR ADC is proposed and prototyped in 0.18 μm CMOS. The supply voltage is scaled down appropriately for different sampling speeds to minimize the power consumption. At a 0.5-V supply voltage and a 100 kS/s sampling rate, the ADC achieves a signal-to-noise and distortion ratio of 56.35 dB and consumes 424 nW, resultin g in a figure of merit of 7.9 fJ/conversion-step...
This paper presents a dual path Nuclear Magnetic Resonance (NMR) receiver dedicated to low cost NMR bio-molecular spectroscopy. Herein we present the design and implementation of CMOS based NMR receiver consisting of an integrated circuit (IC) incorporated with four mini-Coils for NMR exciting and recording purposes. The proposed 21 MHz CMOS receiver consists of differential low-noise amplifiers (LNAs),...
In comparison with conventional operational amplifier, ring amplifier can achieve better power efficiency for switched capacitor circuits. However, the cascade-inverter architecture of ring amplifier may suffer from undesirable oscillation which has a great impact on transient stability. This paper presents a latched-based ring amplifier which is capable of decreasing the probability of oscillation...
The proposed integrated design of WuRx front-end with bandpass filter and frequency synthesizer applying in dedicated biomedical systems has been successfully implemented. The aperture phase detector and phase to analog converter has low power frequency synthesizer might be a promising wireless electrical power source and including wake up receiver technology using direct active RF detection for biomedical...
We present a mixed-signal PA with real-time Class-G and dynamic load trajectory manipulation (DLTM) hybrid operations to achieve PA efficiency enhancement up to the deep power back-off (PBO) region. Moreover, the PA load trajectory is dynamically manipulated to achieve PA efficiency peaking during the PBO operation, and the PA load modulation network is realized by only one on-chip transformer balun...
In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded...
Many existing XOR-XNOR cells suffer from nonfull-swing outputs, high power consumption and low speed issues. In this paper, a new fast, full-swing and low-power XOR-XNOR cell, is presented. Simulation results in 90-nm CMOS technology show that the proposed circuit has rail to rail outputs Also, we have gained 11%–51%, 2%–19% and 18%–52% improvement in delay, power consumption and power-delay product...
This paper presents a generic model that links the compensation techniques used in two-stage amplifiers to the structures of three-stage amplifiers. Many previous designs can be derived from this model, and new three-stage amplifiers can potentially be constructed. A novel three-stage amplifier based on this generic model is proposed. Simulation results show that the proposed design outperforms many...
A low-power low-noise chopper operational amplifier for biosensor applications is proposed. It employs a simple ripple suppression method using a band-pass amplifier. The input referred noise is only 43nV/rtHz. Fabricated in a 130nm standard CMOS process, it occupies a chip area of 0.28mm2 and consumes 33ßA from a 1.2V supply.
High speed silicon optical modulators must be compatible with CMOS drivers to reach their full potential for low cost and low power consumption. We designed a CMOS driver for a Mach-Zehnder modulator (MZM) that has been segmented to lower required voltage swings on a per segment basis and to increase the speed. Previous inductor-less drivers produced on the same process, IBM 130 nm CMOS, ran at 10...
Analog-to-Digital Converts (ADC) are becoming essential to the function of ultra-high speed interconnects (IO) with complex modulation schemes, while at the same time reduction in supply voltage has negatively impacted the performance of such circuits. However the improvement in delay times and reduction in logic size has made time-based ADCs attractive. To accomplish this, a Voltage-to-Time Converter...
A comparator-based circuit that uses switched-capacitor charging replaces the op amp in the multiplying digital-to-analog converter (MDAC) of a low-voltage algorithmic ADC. MDAC output swing beyond Vdd allows greater than rail-to-rail ADC input range. At a supply voltage of 0.55 V, the ADC achieves 8.4 bit ENOB and 1.4 Vpp differential input range. It occupies 0.65 mm2 in 0.25-μm CMOS and dissipates...
Recently, we proposed a low-granularity back-bias control technique [1] optimized for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The technique was preliminary evaluated through the design of a low-voltage 8-bit ripple carry adder (RCA), showing very competitive energy and delay values. In this paper, the characteristics of the low-granularity back-biasing...
Consider the structure of a self-oscillation power amplifier as a power line driver. Self-oscillation power amplifier was improved by the Class-D power amplifier. The traditional Class-D switching power amplifier is vulnerable to distortion limitation. Due to the non-linear continuous time nature of the self-oscillation, it possesses peculiar properties that enable the construction of a highly linear,...
It has been made clear that the presence of hot carriers triggers a series of physical processes that affects the FD-SOI and FinFET device characteristics under normal circuit operation. These effects cumulatively build up over prolonged periods, causing the circuit to age with time, resulting in performance degradations that may eventually lead to circuit failure. In this paper we tackle with the...
The Internet of Things (IoT) became superior innovation area for nanoelectronic circuit design. This work is focused on a multi-modal power gating design approach for sensor node systems for IoT. Power gating is very efficient and flexible way for minimization of IoT CMOS circuits power consumption. However, only a very few papers suggesting multi-modal approach were published. Conventional power...
Using terahertz waves for imaging is gaining increased interest. A CMOS cascode amplifier biased near the threshold voltage of a MOSFET for terahertz direct detection is proposed. A test chip composed of 4×4 pixel CMOS terahertz imaging array is designed and fabricated on the basis of a low-cost 180-nm CMOS process technology. Each pixel consists of a microstrip patch antenna, an impedance-matching...
We systematically analyzed that the "dark-gate" defects were detected by e-beam and bright field inspection as one of the top yield limiters (i.e. the defects of gate-to-contact shorts/leakage) and correlated these to physical failure modes in multiple steps through RMG and MOL process steps. A few effective/novel solutions in the process steps are successfully demonstrated with planar CMOS...
In the advanced nodes of 28nm and below, small defects too can have a significant impact on the final yield results of wafers. As the technology node advances it has become increasingly challenging to control the extent of defects while also ensuring that the desired processing parameters are in place. In this paper we evaluate the influence of various processing parameters on the extent of "Unwanted...
Implanted devices in the brain are required for in-vivo experiments with freely moving animals and will become a key element of future neuronal interfaces, e.g. for prosthetic limbs with neural control. To maintain an optimal signal quality and cope with micro motions of the implant or plastic reorganization of the brain, the concept of electronic depth control was developed. It combines the high...
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