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Specific architectures for different low level vision modalities have been developed and described using reconfigurable hardware. Each of them tries to solve a single low level vision problem: optical flow, disparity, segmentation, tracking, etc. We introduce a novel architecture that includes multiple processing engines in a massively parallel low level vision processing engine of very high complexity...
This paper discusses the use of self-organizing map (SOM) in the image coding. The image is partitioned into blocks each of which is fed to the SOM as the training vectors. Then they are quantized into smaller number of vectors that is used as codeword to reconstruct the image. Thus the data size is reduced. In reconstructing the image, each block is filled with the corresponding codeword. The feasibility...
Xilinx and Mathworks jointly proposed System Generator (SysGen) and Simulink to accelerate development of DSP (digital signal processing) style applications on Field Programmable Gate Array (FPGA) chips. However, most of developments with Simulink and SysGen end at simulation stage without complete stand-alone implementation on FPGA since these tools do not come up with sufficient IO system libraries...
Camera networks are important in a video surveillance system. Many surveillance systems research has been done; most of it utilizes a general purpose computer. However, the latest trend is to use small, task specific and low power computer to process and control the system; in another word using embedded systems. This paper presents a camera network localization algorithm to be implemented on a FPGA...
Real-time video processing is the basic requirement for applications such as video surveillance, traffic management and medical imaging. The high computation power is a requirement to support this operation. This requirement could be fulfilled by utilizing the hardware accelerator architecture for computation part. This paper presents the development of edge detection hardware accelerator architecture...
The emerging H.264 SVC (Scalable Video Coding) standard specifies an encoder solution responsible for generating a multi-layer stream, which provides extra flexibility for modern multimedia applications. The increased data dependency among different layers demands a significant overall encoder performance. Aiming the use of an SVC solution in real-time applications we propose an optimized hardware...
We present a real-time multi-sensor architecture for video-based pedestrian detection used within a road side unit for intersection assistance. The entire system is implemented on available PC hardware, combining a frame grabber board with embedded FPGA and a graphics card into a powerful processing network. Giving classification performance top priority, we use HOG descriptors with a Gaussian kernel...
In this paper we study the implementation of correcting projection distortion due to the curved display. The studied display is the lateral surface of a cylindroid with known parameters. Firstly we introduce the mapping function by which the image is pre-processed before it is projected. We then reconsider the formula in the hardware calculation point of view and develop an algorithm that can be executed...
Prediction, including intra prediction and inter prediction, is the most critical issue in H.264 decoding in terms of processing cycles and computation complexity. These two predictions demand a huge number of memory accesses and the total decoding cycles. In this paper, an efficient hardware architecture for real-time implementation of intra and inter predictions algorithm used in H.264 video coding...
This paper presents an efficient real-time implementation of an unsupervised textile fabric defect detection algorithm called ITT using the concept of iterative tensor tracking on graphics processing unit (GPU). The algorithm adopts a new local image descriptor, Spatial Histograms of Oriented Gradients (S-HOG), which is shift-invariant, light insensitive and space scalable. For a given textile fabric...
FPGAs provide a flexible architecture for implementing many different types of machine vision algorithms. They allow heavily parallel portions of those algorithms to be accelerated and optimized for high specific performance (MIPS:Watt ratio). In comparison to ASICS, FPGAs enable low cost, quick turn prototyping and algorithm development as well as lower production costs for small quantity and one...
Fractional motion estimation (FME) is an important part of the H.264/AVC video encoding standard. The algorithm can significantly increase the compression ratio of video encoders while at the same time improve video quality. The FME algorithm, however, is also computationally expensive and can consist of over 45% of the total motion estimation process. To maximize the performance and efficiency of...
The High-energy Stereoscopic System (H.E.S.S.) is an array of atmospheric Cherenkov telescopes dedicated to GeV-TeV γ ray astronomy. Four 12 meter diameter telescopes (CT) are currently in operation and a fifth 28 meter diameter telescope (LCT) should be completed by 2011. This will lower the system's energy threshold in stereoscopy down to ≈ 50 GeV. Concurrently, the LCT will also be used to detect...
Since December 2009, the Large Hadron Collider (LHC) and its four main experiments are taking physics data. Each of those four experiments consists of sub-detectors, which are responsible for energy, momentum and particle trajectory measurements. As the innermost sub-detector of the ATLAS experiment, the Pixel detector provides precise measurements of momenta and trajectories of charged particles,...
The objective of this work is to design and implement an Image and Video Processing Platform (IVPP) on FGPAs using PICO based HLS. This hardware/software codesign platform has been implemented on a Xilinx Virtex-5 FPGA. The video interface blocks are done in RTL and the initialization phase is done using a MicroBlaze processor allowing the support of multiple video resolutions. This paper discusses...
A low power competitive fuzzy edge detection (C-FED) processor is proposed for gradient calculations in volume rendering. Its linearized fuzzy membership function reduces overall power by 35.1% and the proposed hardware sharing between computation stages reduces power consumption by 18%. Threshold adaptive bit control scheme is proposed to predetermine background pixel with simple operation which...
This paper discusses some new suggestions for designing hardware vision systems that take inspiration from spike-based biological image processing. The key idea is to modify already existing Address Event Representation (AER) designs so that there is a periodic reset signal that can be generated every time some predefined proportion of "neurons" has emitted a spike. Each "neuron"...
Hardware-and-software full system co-verification and co-simulation in the early stage of SoC development, i.e., before HDL code synthesis, is usually a big challenge for design engineers. In this paper, we propose a QEMU-based full system simulation framework to tackle the problem faced with the design of an embedded multi-view 3D GPU (graphic processing unit). Through the framework, we are able...
As the history of television industry goes, multiview video (MW) and its applications draw more and more attentions by the realistic 3D scene it can bring. In these applications, virtual view synthesis is required for providing free view point sequences so as to fulfill a real-time display system. In this paper, a low-area architecture is proposed. By employing the linear-interpolated approximation...
Three-dimensional television (3D-TV) has attracted significant attention because of 3D immersive feeling for advanced TV development. Multi-view rendering by depth image based rendering (DIBR) and interlacing are the key technologies to realize 3D-TV system from content to display. In this paper, a new multi-view rendering hardware architecture consisting of hybrid parallel DBIR and pipeline interlacing...
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