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This paper proposes a performance-conscious reconfiguration structure to accelerate the reconfiguration process in a high efficient coarse-grained reconfigurable system called Reconfigurable Array Template Version-I (RAT-I). To meet the high requirements of reconfiguration performance for large-scale reconfigurable systems, the hierarchical storage structure of configurations together with the configuration...
Modern-day streaming digital signal processing (DSP) applications are often accompanied by real-time requirements. In addition, they expose increasing levels of dynamic behavior. Dynamic dataflow models of computation (MoCs) have been introduced to model and analyze such applications. Parametrized dataflow MoCs are an important subclass of dynamic dataflow MoCs because they integrate dynamic parameters...
The novel High Efficiency Video Coding (HEVC) standard targets a broad set of different video formats ranging from QVGA up to Ultra-HD (4Kp60) resolutions. Especially the high spatial and temporal resolutions combined with the high algorithmic complexity makes implementing encoders and decoders a challenging task. Existing software based implementations on multi-core CPUs and/or DSPs suffer from real-time...
Using the structure of FPGA and DSP to achieve real-time image processing system, Preprocessing the camera data with FPGA running speed and parallel processing ability and compressing transmission image by DSP. In the process of the image data of the dark, using the logarithm stretching algorithm, Increasing the image enhancement module, the image brightness uneven distribution becomes clear. Using...
A fuzzy rate control algorithm (RCA) with buffer constraint is presented for H.264/SVC standard with independently controlling each layer. By calculating the variation of quantization parameter (QP) instead of QP itself on group of pictures (GOP) level, this algorithm can be used efficiently for video streaming applications. The initial buffering in these applications allows slight variations in bit...
Efficient transport schemes for panoramic video delivery were proposed and demonstrated within the past decade. With the recent advances of head mounted displays however, consumers may soon have immersive and sufficiently convenient end devices at reach which could lead to an increasing demand for stereoscopic panoramic video experiences. This paper extents recent compressed domain techniques for...
Partial dynamic reconfiguration of FPGAs can be used to implement complex applications using the concept of virtual hardware. In this work we have used partial dynamic reconfiguration to implement a JPEG decoder with reduced area. The image decoding process was adapted to be implemented on the FPGA fabric using this technique. The architecture was tested in a low cost ZYNQ-7020 FPGA that supports...
This paper shows how the decoding energy of HEVC software decoders can be estimated when using high-level features of a coded bit stream. The investigated features comprise number of frames, resolution, bitrate, QP, and encoder configuration, where the proposed model reaches an average estimation error of 10%. While establishing this model, we closely investigated the influence of these high-level...
According to published literature for turbo decoding, SOVA and log-MAP algorithms share common operations. This paper shows that the improved reconfigurable SOVA/log-MAP turbo decoder can be implemented in LTE standard for uncorrelated Rayleigh fading channel. We concentrate on physical shared channel and use pipeline turbo decoder architecture with 12 iterations. We examine two data rates and for...
Some video applications work with parallel bitstreams however only parts of them are required. Decoding the streams entirely might be prohibitive due to high number of video streams and / or high resolution or bitrate of the streams. In such cases, a random access also referred as to partial decoding has to be supported. It can be achieved with a conforming decoder, if the video is separated into...
In this paper, we have implemented a dynamic pipeline-partitioning video decoder for the symmetric stream multiprocessor (SSMP) architecture. The SSMP architecture extends the traditional symmetric multiprocessor (SMP) architecture with dedicated per-core scratchpad memories and inter-processor communication (IPC) controllers for efficient data passing between the processor cores. The SSMP architecture...
Hard-real time video systems require deterministic admission control decisions to maintain high levels of predictability. These decisions can be based on the state-of-the-art schedulability analysis of tasks and flows. However, due to the pessimistic behaviour of the schedulability analysis and the uncertainties in the application, the multi-core system resources are usually under-utilised. In this...
High Efficiency Video Coding (HEVC) is the new video compression standard, reducing bitrates nearly at half compared to H.264, offering potentially significant power savings for wireless video transmission at the network interface. This reduction in bitrate is achieved by a series of computationally expensive algorithms, thus making imperative to optimize HEVC decoding in order to provide a low-power...
Software video decoders for mobile devices are now a reality thanks to recent advances in Systems-on-Chip (SoC). The challenge has now moved to designing energy efficient systems. In this paper, we propose a light Dynamic Voltage Frequency Scaling (DVFS)-enabled software adapted to the much varying processing load of High Efficiency Video Coding (HEVC) real-time decoding. We analyze a practical evaluation...
Band Codes (BC) have been recently proposed as a solution for controlled-complexity random Network Coding (NC) in mobile applications, where energy consumption is a major concern. In this paper, we investigate the potential of BC in a peer-to-peer video streaming scenario where malicious and honest nodes coexists. Malicious nodes launch the so called pollution attack by randomly modifying the content...
Long Term Evolution (LTE) has been standardized at the 3GPP since 2008 and targets the delivery of high data rate services with strict quality-of-service (QoS) requirements. It is now the fastest ever growing mobile technology and is gradually becoming the mainstream radio access technology used in cellular networks. The latest video coding standard, High Efficiency Video Coding (HEVC), achieves higher...
In wireless video broadcast system, analog joint source-channel coding (JSCC) has shown advantage compared to conventional separate digital source/channel coding in the aspect that it can avoid cliff effect gracefully. What's more, analog JSCC only needs a little calculations at the encoder and has strong adaptability to different channel condition, which is very suitable to the wireless cooperative...
The rapid growth of video in wireless networks is a crucial issue to be addressed by content providers. Nowadays, an emerging and promising trend is the development of solutions aimed at maximizing the quality of experience (QoE) of end users. However, the prediction of the QoE perceived by users in different conditions remains a major challenge. In this paper, we propose a two-layer hierarchical...
A 4K and Main-10 HEVC video decoder LSI is fabricated in a 28nm CMOS process. It adopts a block-concealed processor (BcP) to improve the visual quality and a bandwidth-suppressed processor (BsP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. It features fully core scalable (FCS) architecture which lowers the required working frequency...
Complexity of both, applications and processors, is permanently increasing. While, designers must face with a lot of challenges, such as reduced time to market, performance and energy efficiency, among others. In this context, dataflow based methodologies and tools, like the Open RVC-CAL Compiler Infrastructure (Orcc), have revealed powerful in supporting platform independent design. Within the Orcc...
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