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We live in interesting times. Our systems have unprecedented levels of device integration. Analog and mixed signal components and devices form increasingly large parts of our designs built for low power and high flexibility. New architectures and models of computation that embrace variation like neuromorphic computing are a part of our horizon. Architectures specialized for neural networks and learning...
A variety of architectures have been proposed for neuromorphic computing chips, including digital, analog, and memristor based approaches. The application space used to analyze these designs is typically narrow, focused primarily on natural signal processing tasks such as image or audio classification. In this work, we analyze the ability of a memristor-based neuromorphic architecture to perform tasks...
This study investigates the effect of image rescaling and format changing hosted in a RESTful API architecture considering transfer time as a critical factor to apply lane detection on a external server. We employ Probabilistic Hough Transform to perform the detection because it is invariant to pixel position and robust to noise. Before being trasmitted to the external server, images are rescaled...
DNA is considered as a good computing device because of the predictability of the double helical structure and the Watson-Crick binding thermodynamics associated with them. DNA circuits can be considered as a possible replacement of silicon transistor based circuits, in implantable medical devices, bio-nanorobots, SMART drugs etc. In this paper, we are proposing a novel five input majority logic gate...
With the death of Moore's law, the computing community is in a period of exploration, focusing on novel computing devices, paradigms, and techniques for programming. The TENN-Lab group has developed a hardware/software co- design framework for this exploration, on which we perform research with three thrusts: (1) Devices for computing, such as memristors and biomimetic membranes. (2) Applications...
Recent advances in the development of commercial quantum annealers such as the D-Wave 2X allow solving NP-hard optimization problems that can be expressed as quadratic unconstrained binary programs. However, the relatively small number of available qubits (around 1000 for the D-Wave 2X quantum annealer) poses a severe limitation to the range of problems that can be solved. This paper explores the...
The deceleration of transistor feature size scaling has motivated growing adoption of specialized accelerators implemented as GPUs, FPGAs, ASICs, and more recently new types of computing such as neuromorphic, bio-inspired, ultra low energy, reversible, stochastic, optical, quantum, combinations, and others unforeseen. There is a tension between specialization and generalization, with the current state...
In the near future, one of the main processes is solving large combinatorial optimization problems. However, the performance growth of von Neumann architecture will slow due to the end of semiconductor scaling. To resolve this problem, we propose an Ising computer that maps the optimization problems to the ground state search of Ising models. We previously proposed a computer that finds the ground...
In this paper, we propose VoiceHD, a novel speech recognition technique based on brain-inspired hyperdimensional(HD) computing. VoiceHD maps preprocessed voice signals in the frequency domain to random hypervectors and combines them to compute a hypervector (as learned patterns) representing each class. During inference, VoiceHD similarly computes a query hypervector; the classification task is done...
The use of GPU in point cloud processing usually represents a gain in computation time more than ten times higher then on CPU, especially for large amounts of data. This paper brings an evaluation of the processing time for point cloud fusion in three different systems (PC, Nvidia TX1 and Nvidia TK1) using CPU and GPU. The objective is to find the best way to perform sensor fusion for an autonomous...
Provided by Google, Eddystone standard consists of a beacon technology, open-source format, unidirectional and proximity-based Bluetooth® Low Energy (BLE) standard. Eddystone can support multiple different payloads, portable for IOS and Android with a ranging of approximately 50 meters. This paper analyses different metrics of a Verilog digital logical implementation of a Google Eddystone...
This paper proposes an approach to optimize service placement on Fog landscape in the context of the Internet of Things (IoT). A multi-tier fog computing architecture that supports IoT service provision is devised. Based on this architecture, a novel service placement mechanism that optimizes service decentralization on Fog landscape leveraging context-aware information such as location, time, quality...
In many-core systems, the processing elements are interconnected using Networks-on-Chip. An example of on-chip network is SoCIN, a low-cost interconnect architecture whose original design did not take into account security aspects. This network is vulnerable to eavesdropping and spoofing attacks, what limits its use in systems that require security. This work addresses this issue and aims to ensure...
Current solutions for sensor-cloud integration do not offer tools or platforms providing both efficient data management and standardized interfaces for the development of WSN-based applications on a shared infrastructure. This paper proposes a new architecture based on the paradigm of Service-Oriented Computing and virtualization of sensors for efficient management of heterogeneous WSNs data. The...
Hardware-in-the-Loop Simulation is being increasingly used in verification and validation of embedded computer systems; as well as for rapid prototyping and validation of models. The numerous benefits of this technique and the possibility of widespread use is hindered by the high cost of the necessary infrastructure. The proposed solution is based on a PC executing the plant simulation and connected,...
Recently, the SDN paradigm, which splits the control and data planes, initially defined for wired networks, has been considered as a solution for the management of WSNs (Wireless Sensor Networks). However, the adoption of OpenFlow protocol, the most widely deployed SDN standard, directly into the WSNs may require novel / customized hardware or incur significant signaling overhead. This paper proposes...
With the fast increasingly use of image and video processing in many aspects, the requirements for high performance and high-quality systems lead to the use of reconfigurable computing to accelerate traditional image processing platforms. In this work, an efficient runtime adaptable floating-point Gaussian filtering core is proposed to achieve not only high performance and quality but also kernel...
Neuromorphic computing takes inspiration from how the brain works to explore novel computing paradigms. Recently, neuromorphic architectures using spiking neurons were proposed for unsupervised learning of pattern- and feature-based representations. These approaches typically use a common WTA architectural motif of lateral inhibition that introduces competition between the neurons. In this paper,...
Unlike general purpose computer architectures that are comprised of complex processor cores and sequential computation, the brain is innately parallel and contains highly complex connections between computational units (neurons). Key to the architecture of the brain is a functionality enabled by the combined effect of spiking communication and sparse connectivity with unique variable efficacies and...
Gene Expression Networks (GENs) attempt to model how genetic information stored in the DNA (Genotype) results in the synthesis of proteins, and consequently, the physical traits of an organism (Phenotype). Deciphering GENs plays an important role in a wide range of applications from genetic studies of the origins of life to personalized healthcare. Probabilistic graphical models such as Bayesian Networks...
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