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A low-power FMCW 80 GHz radar transmitter front-end chip is presented, which was fabricated in a SiGe bipolar production technology ( , ). Additionally to the fundamental 80 GHz VCO <citerefgrp><citeref refid="ref1"/></citerefgrp>, a 4:1-frequency divider (up to 100 GHz), a 23 GHz local oscillator (VCO) with a low phase...
Today, the current need consisting of implementing more and more complex systems imply the implementation of new methodologies to make the CAD product reliable in order to improve time to market, study costs, reusability and reliability of the design process. This paper proposes a high level design approach applied for the simulation and the optimization of fractional-N synthesizer acting as a direct...
A 1.2 V 60 GHz 120 mW phase-locked loop employing a quadrature differential voltage-controlled oscillator, a programmable charge pump, and a frequency quadrupler is presented. Implemented in a 90 m CMOS process and operating at 60 GHz with a 1.2 V supply, the PLL achieves a phase noise of −91 dBc/Hz at a frequency offset of 1 MHz.
The coupling of oscillators is reviewed. A new scheme of coupling of VCOs is proposed in which no extra elements are needed to couple the VCOs, which leads to a lower phase noise and power consumption. Based on simulation results, a lock-in range from 15.7 GHz to 18.7 GHz for a divide-by-3, and from 16.4 GHz to 17 GHz for a divide-by-5 were achieved with a 180 nm CMOS technology with a Vdd=1.8 V.
We present a photonic method for tunable high frequency carrier generation and wideband tunable RF frequency down-conversion with low phase noise. The phase noise of the photonic generated RF/IF signal is limited by the RF signal generator used to synthesize the optical local oscillators. We show phase noise measurements of photonic frequency synthesized carriers at 24 GHz and down-conversion measurements...
This paper presents the design and experimental verification of a W-band phase-locked loop (PLL) realized in 65-nm digital CMOS process. The PLL incorporates the proposed divide-by-three frequency divider to relax the power/speed requirement for the succeeding divider chain. A distributed-LC tank is employed in the VCO as well, improving the tank quality factor and the circuit speed. Thus, the power...
Frequency multiplication by 3/2 is proposed as a means to expand the frequency generation capabilities of a single LC VCO. Fractional frequency multiplication is obtained by cascading a broadband injection locked modulo-two divider and a multiply-by-three circuit based on edge combining. The proposed solution is inductorless, thus very compact. It allows the generation of all frequencies from 2.7...
Absolute phase noise < −100 dBc/Hz at 1 Hz offset from a 10 GHz carrier is demonstrated by using an Er:fiber frequency comb to frequency-divide a narrow linewidth CW laser.
We present a 220 GHz fundamental PLL, based on a 220 GHz VCO, 2:1 dynamic frequency divider, fifth-order sub-harmonic phase detector, active loop filter, and output amplifier, fabricated in an InP HBT technology. The measured PLL locking range was 220.0 to 225.9 GHz, with -83 dBc/Hz of phase noise at a 100 KHz offset, while consuming 465.3 mW. The PLL occupies 1.1 mm2 including pads.
We proposed a voltage-controlled oscillator (VCO) and an injection-locked frequency divider (ILFD) at a stacking topology. The proposed circuit has its optimized performance and low power consumption. The circuit was designed in a 0.13 µm CMOS technology. The VCO's output frequency is from 11.2 GHz to 13.4 GHz while the ILFD's output frequency is from 5.6 GHz to 6.7 GHz. The total power consumption...
The mathematical analysis of a hybrid method of frequency synthesis is carried out, allowing theoretically to estimate level of noise components. Power spectral densities of a phase noise of an output signal of a hybrid synthesizer of frequencies are calculated. Comparison of level of the noise components received experimentally and theoretical is made.
A wideband low power CML frequency divider suitable for the Ku band has been designed and fabricated in a 90nm CMOS technology. Simulated phase noise and sensitivity curves are validated through on-wafer probe measurements. The maximum operating frequency is 24 GHz while dissipating 2.25 mW from a 1.5 V supply, resulting in a power-delay product of just 11.7 fJ. The divider measures 34 µm × 42 µm,...
This paper reports comparisons between RTW VCO and LC QVCO 12 GHz PLLs, designed in a 130 nm CMOS technology. The phase noise at 1MHz offset from the carrier is −102 dBc/Hz for the RTW VCO PLL and −98 dBc/Hz for the LC QVCO PLL, and the power consumption is 39mW and 17 mW, respectively.
A fully integrated integer-N frequency synthesizer has been designed and implemented in 0.18μm RF CMOS technology for low intermediate frequency (IF) ZigBee transceiver application. It incorporates an automatic frequency calibration (AFC) loop to extend frequency tuning range. In-phase and quadrature (IQ) signals are generated by a divide-by-two frequency divider at the output of PLL. It consumes...
A fully integrated dual-loop PLL for mm-wave applications is presented. The design includes a phase locked hold loop and a frequency acquisition loop; by using two types of phase detectors for each individual loop, a low phase noise, a fast lock time, and a wide locking range can be achieved simultaneously. A method for phase noise optimization of the PLL is described. The chip was designed in a 250...
We present a 300 GHz fundamental PLL, based on a 300 GHz VCO, 2:1 dynamic frequency divider, fifth-order sub-harmonic phase detector, and active loop filter, fabricated in an InP HBT technology. The PLL achieves locking from 300.76 to 301.12 GHz, with −23 dBm of output power and −78 dBc/Hz of phase noise at a 100 KHz offset, while consuming 301.6 mW. The PLL occupies 0.84 mm2 including pads. This...
This paper presents two all-digital RF frequency synthesizers implemented in 65-nm CMOS: a digital period frequency synthesizer and an all-digital phase-locked loop. This paper is especially focused on the implementation issues and practical challenges of digital frequency synthesizers for wideband radio systems. Moreover, the paper presents implementations and experimental results of these two frequency...
A 2.5 GHz low power current reused Colpitts VCO and divide-by-two circuit is proposed in 0.18µm CMOS technology. The divider is stacked on top of a common drain gm-boosted differential Colpitts VCO to share the DC current. A parasitic capacitance neutralization technique is used to eliminate the miller effect with the VCO, and improves the generated negative resistance and phase noise performance...
An active inductor oscillator-based divide-by-3 injection locked frequency divider (ILFD) is proposed, and was implemented in the 0.35 μm SiGe 3P3M BiCMOS technology. Measurement results show that when the supply voltage Vdd is biased at 3.0 V, the free-running oscillation frequency of the ILFD is tunable from 3.84 GHz to 3.13 GHz, and at the incident power of 0 dBm and the Vtune = 2.5 V, the locking...
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