The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Following the decision to choose Rijndael as the successor of Data Encryption Standard (DES), Advanced Encryption Standard (AES) was increasingly used in numerous applications which require confidentiality and the secure exchange of the data. While security is a property increasingly sought for many applications (credit cards, telecommunications …), it becomes necessary to consider physical attacks...
The cryptographic hash algorithm has been developed by designers with the goal to enhance its performances in terms of frequency, throughput, power consumption and area. The cryptographic hash algorithm is implemented in many embedded systems to ensure security. It is become the default choice to ensure the information integrity in numerous applications. In this paper, we propose a pipelined architecture...
With network traffic rates continuously growing, security systems like firewalls are facing increasing challenges to process incoming packets at line speed without sacrificing protection. Accordingly, specialized hardware firewalls are increasingly used in high-speed environments. Hardware solutions, though, are inherently limited in terms of the complexity of the policies they can implement, often...
A multi-mode QC-LDPC decoder is proposed to satisfy the 802.11n/ac WiFi standard. With code-specific design, the overall performance of the decoder is enhanced while ensuring an on-the-fly reconfigurable ability. The proposed architecture has been synthesized using an FPGA for measurements. A state-of-art error rate and implementation complexity are reported. Meanwhile, the throughput has been increased...
In accordance with the past trend of technological advancements in hardware implementation of security mechanisms, there is an ongoing decrease in size of cryptographic systems with increase in low power and high throughput constraints. In this paper, we present a novel 8-bit pipelined architecture for Advanced Encryption Standard (AES) which ensures high throughput with low area and power consumption...
As network technology advances, information security issues increase the need for developing low-area and low-power high performance real-time processing of cryptographic algorithms. In this paper, we present a novel 8-bit architecture for Advanced Encryption Standard (AES) encryption which supports keys of 128-bit in length. The proposed architecture consists of a single round of ShiftRows, ByteSubstitution,...
Detecting heavy activity aggregation in data streams is a critical task for many networking, data base and data-mining applications. The aggregation points often belong to hierarchical domains (e.g. IP domain, XML data tree, etc.). These aggregation points are referred to as hierarchical heavy hitters. The hierarchical domains is usually very large with respect to both the number of aggregation points...
The Advanced Encryption Standard (AES) together with the Galois Counter Mode (GCM) of operation has been approved for use in several high throughput network protocols to provide authenticated encryption. However, the demand for continued increase in network bandwidth has not abated and we anticipate the need for continual performance improvement of AES-GCM in hardware. Additionally, as data interfaces...
With the exponential growth of data size, data storage and analysis have been exposed to more challenges due to the lack of disk capacity and the limited network bandwidth. Data compression technique provides a good solution to mitigate these effects. In this paper, we propose a self-aware data compression system on FPGA for typical data warehousing, such as Hive, with column stored data and multi-threading...
In this paper, we present a novel co-designed architecture for high throughput database query processing. It consists of a highly configurable FPGA-based filter chain with arithmetic operation support and an alignment unit. This feeds the filtered data directly and in a cache-optimized way to embedded processors which are responsible for joining tables and post processing. High throughput interfaces...
Sorting is a key kernel in numerous big data application including database operations, graphs and text analytics. Due to low control overhead, parallel bitonic sorting networks are usually employed for hardware implementations to accelerate sorting. Although a typical implementation of merge sort network can lead to low latency and small memory usage, it suffers from low throughput due to the lack...
In recent years, high-level languages and compilers, such as OpenCL have improved both productivity and FPGA adoption on a wider scale. One of the challenges in the design of high-performance stream FPGA applications is iterative manual optimization of the numerous application buffers (e.g., arrays, FIFOs and scratch-pads). First, to achieve the desired throughput, the programmer faces the burden...
Significant changes in traffic patterns often indicate network anomalies. Detecting these changes rapidly and accurately is a critical task for network security. Due to the large number of network users and the high throughput requirement of today’s networks, traditional per-item-state techniques are either too expensive when implemented using fast storage devices (such as SRAM) or too slow when implemented...
With the rapid increase of the network bandwidth, to process high throughput regular expressions with hardware has become inevitable. This paper presents a novel NFA-based algorithm. In this paper, two theorems were proved and were used to prove the correctness of the algorithm. Our approach was based on three basic modules to construct NFA that can be easily reused in a FPGA or ASIC. The quantitative...
CRC (Cyclic Redundancy Check) is a simple and an elegant method for error detection. It finds application in most of the high-speed data communication protocol. In High Energy Physics experiment often CRC is used for control and data frame communication with detectors placed at radiation zone. Reliability of CRC error detection capability alters with generator polynomial chosen. The most popular choice...
One of the most calculation intensive operations for a 100 Gbps wireless packet processing is a forward error correction (FEC). We are using standard field programmable gate arrays (FPGAs) to prepare a data link layer demonstrator. Therefore, we need to find a high-parallelized FEC structure for our device. The difficulty is to design the 100 Gbps FEC engine that can be realized in an FPGA. In one...
We propose a design to aid experimentation with SDN architectures using legacy network equipment. We implement a portion of the design on an FPGA and evaluate throughput and latency. Results indicate viability for testbed and research environments, especially with proposed additions to further reduce latency in broadcast- and multicast-heavy traffic.
Today's applications and services become more dependent on fast wireless communication, for the upcoming years data-rate demands of 100Gbit/s can be easily expected. However, fulfilling that demand is a task which cannot simply be solved by upscaling existing technologies. While most of the research tackles the challenges regarding the transmission technology from the physical layer up to base-band...
The increasing data rates expected to be of the order of Gb/s for future wireless systems directly impact the throughput requirements of the modulation and coding systems of the physical layer. In an effort to design a suitable channel coding solution for 5G wireless systems, in this brief we present two approaches to improve the throughput of a Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder...
The paper is devoted to design of the digital components for safety-related instrumentation and control systems using the modern CAD tools. Traditionally, the digital components are built with matrix parallelism that reduces fault tolerance of circuits and safety of systems in their checkability. Circuits with bitwise pipeline data processing have advantage in checkability, but are considered as less...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.