The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A single event latchup protection switch (SPS) has been developed in the IHP 250 nm bulk CMOS technology. The SPS has been designed as a standard library cell intended for implementation in the radiation-tolerant application specific integrated circuits (ASICs). It provides detection of single event latchup and subsequent shut-down of power supply to critical elements within the chip to restore the...
Threshold Inverter Quantizer (TIQ) based ADC with thermometer code is proposed in the literature as an alternative to traditional flash ADC for low power applications. TIQ based ADC suffers from threshold variations due to process. In this paper, a novel TIQ based ADC with gray code is proposed.The architecture is also made tolerant to the process variations. For the purpose of evaluating its efficacy,...
Dynamic body-biasing is a well studied approach for reducing the leakage power in memory systems. Proposed designs dynamically change the body bias of the inactive memory cells in order to tune their threshold voltages. However, prior body biasing schemes only focus on the static power reduction and overlook the power dissipation stemmed from the short circuit current. Recent studies showed that the...
Conventional CMOS technology provides a lot of opportunities in the field of electronics device. But presently, carbon nanotube field effect transistor (CNTFET) is a new technology for the application in the field of electronic device. Due to the limitation of the size of CMOS, CNTFETs are the promising substitute due to its nano scale size. CNTFET also shows the high stability, low power circuit...
Recent experiments in the field of VLSI designing and Nanotechnology have demonstrated a working cell suitable for implementing the Quantum-dot Cellular Automata (QCA). QCA is a transistor less computational model which is expected to provide high density nanotechnology implementations of various CMOS circuits. QCA has been constrained by the problem of meta-stable states. QCA adder with comparatively...
This paper investigate the performance of the Universal filter with three input and single output based on Transconductance CMOS Inverter based positive type second generation current conveyor (TCI-CCII+) using two resistors and two capacitors. The filter realizes the three filter responses i.e. Low-pass, High-pass and Band-pass responses due to multiple responses generate by the filter by applying...
To analysis leakage current and delay for Double Gate MOSFET with Single gate MOSFET at 45nm in CMOS Technology by using the Cadence Virtuoso simulation tool. When compared to single gate MOSFET, the leakage current and delay are observed to be reduced in double gate MOSFET. The drive current remains the same for both single and double gate MOSFET based on Vgs but the short channel characteristics...
This paper presents two new Schmitt trigger circuits with eight enhancement-type MOS transistors are introduced in this paper. These two Schmitt trigger circuits are implemented based on current sink and current source inverters. The hysteresis curves of the proposed Schmitt triggers are presented, hysteresis width depends on the supply voltage and transistor geometry. These circuits are preferred...
Physical Unclonable Functions (PUFs) exploits static process variation across integrated circuits in the manufacturing processes to generate many unique, random and unclonable security keys. In this paper, a threshold dominant delay PUFs (TDD-PUFs) is designed in TSMC 65nm CMOS technology. After configuring the nMOSFET and pMOSFET dominant delay, TDD-PUFs updates the key without physically replace...
In this paper, a detailed analysis of the voltage transfer characteristics of vertical nanowire transistor-based CMOS inverter is presented. We show that noise margins are strongly dependent on the source/drain series resistance, and that the extension lengths can be used as tuning parameters to control the noise margin and gains of the inverter.
This paper proposes a 4-bit 6GS/s Time-Based Analog-to-Digital Converter (TADC) to be integrated inside the Software Defined Radio (SDR) receivers. The TADC is mainly composed of two blocks which are the Voltage-to-Time Converter (VTC) and the Time-to-Digital Converter (TDC). A prototype of the proposed TADC is implemented using 65 nm technology with a sampling rate of 6GS/s. An ENOB of 3.68 is achieved...
Multiplier is the most commonly used circuit in digital devices. Multiplication is one of the basic functions used in digital signal processing. Gate Diffusion Input (GDI) logic reduces the power dissipation and area of digital circuits while maintaining low complexity of logic design. In this paper, GDI technique is used for low-power design of 8-bit multiplier. Reduction in power and area can be...
This paper presents an experimental analysis of the impact of AC- and DC-type Negative Bias Temperature Instability (NBTI) stresses on the CMOS inverter DC response and robustness. The results reveal, on one side, that the inverter DC response under AC NBTI presents a parallel shift of that shown under DC NBTI. However, the AC- to DC-induced shift of the inverter logic threshold is found much less...
This paper presents an operational amplifier based on pseudo-CMOS blocks and integrated in a flexible a-IGZO TFT technology. The circuit consists of only nMOS transistors, and the pair of active loads is in a pseudo-CMOS configuration. These active loads allow various kinds of common mode feedback schemes or cross-coupled connection, typical for CMOS operational amplifiers. The proposed amplifier...
We have previously proposed a new digital CMOS circuit which combined subthreshold circuit and adiabatic logic circuit with ultra-low power consumption. Our proposed circuit which is driven by two AC power supply with different frequency and amplitude, and is adapted to be provided a margin of switching timing of input signal. In this paper, we show a skew tolerance analysis of subthreshold adiabatic...
A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode multiple-valued logic(MVL), is proposed. The dynamic ternary inverter, literal circuits, and quaternary inverter are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is solved. The...
In this paper we examine a digitally controllable Nauta structure implemented in a 65nm process and identify a strategy useful for calibrating the structure in such a way that a maximum gain is achieved. We propose an efficient and simple tuning procedure that could be the basis for an integrated on-chip calibration solution and investigate the feasibility of implementing it. The procedure would primarily...
This paper proposes a novel high frequency ring oscillator. The proposed ring oscillator consists of CMOS inverters which use simple capacitor based level shift circuits. The level shift circuit consists of only a capacitor and a MOSFET. Its power consumption is ideally zero. Thanks to the level shift circuits, transconductance and drain conductance of MOSFETs in CMOS inverters increase and high oscillation...
A new reconfigurable linearized low noise transconductance amplifier (LNTA) design for a software-defined radio receiver is presented. The transconductor design aims at realizing high linearity at RF in a way that is robust for Process, Voltage and Temperature variations. It exploits resistive degeneration in combination with a floating battery by-pass circuit and replica biasing to improve IIP3 in...
In this paper, the design of a single-chip RF Pulse-Width Modulator and Driver (PWMD) aimed at exciting a 80 W class-E GaN high-power stage at 435 MHz is described. For the required buffer size, avoiding potential ringing of the pulses within the buffer structure presents a major challenge in the design process. Therefore, a smaller chip capable of driving capacitive loads of up to 5 pF was initially...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.