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This paper describes the new energy saving method for AC motor drive control that is based on self-commutated current inverter with a relay regulator of stator current. Designed inverter is based on IGBT-transistors and contains additional cutting diodes and buffer capacitor blocks. The experimental model of control system and its power circuit are built. Simulation results and oscilloscope curves...
A new modulation strategy with Hysteresis Current Mode Control for Bidirectional Dual Active Bridge (DAB) is proposed in the paper. A simulation model for Buck and Boost mode of operation is developed and implemented in the MATLAB/SIMULINK environment. The value of the calculated leakage inductance is verified using COMSOL program. The proposed Hysteresis Current Mode Control allows combining the...
This paper considers problems related with the switching losses in the power supply units, based on a high frequency inverters. Different ways to overcome some of the problems are discussed. A ZVS gate driver circuit for transistors in resonant DC/DC converter is proposed. The influence of the snubber capacitors value is studied. Experimental results to demonstrate the effectiveness of the driver...
The paper presents fault tolerant control algorithms of modified space vector pulse width modulation (SVPWM) for three-phase inverter supplies a PMSM in case of failure of one transistor leg. Fault tolerant inverter structure with four-switch is analyzed with taking into account the non-ideal DC link. Calculations of the desired voltage vector in the PMSM drive are presented. An optimal voltage vector...
We propose a non-redundant Flip-Flop (FF) with stacked transistors based on Adaptive Coupling Flip-Flop (ACFF) with lower power consumption in a 65 nm Fully Depleted Silicon On Insulator (FDSOI) process. The slave latch in ACFF is much weaker against soft errors than the master latch. We design several FFs with stacked transistors in the master or slave latches. We investigate radiation hardness of...
Muller C-element is one of the main parts of an asynchronous circuit. Being sequential by its nature, it is vulnerable to single event upsets (SEU). We propose three 65 nm CMOS circuit implementations of SEU tolerant C-element, whose tolerance is achieved by using of well-known DICE principle and is proved by SPICE simulations and semi-empirical estimations.
In this paper, the utility of double-gate (DG) junctionless (JL) transistor in attaining better DC and analog/RF performances are demonstrated. The analysis is done by extracting drain current versus gate voltage characteristics, transconductance (gm), transconductance generation efficiency (gm/Ids), gate-to-gate capacitance (Cgg), ratio of gate-to-source capacitance (Cgs) to gate-to-drain capacitance...
An ultra-low power voltage-to-time converter (VTC) circuit is proposed. The VTC circuit is compatible with wide range of applications (i.e. sensors, integrated DC-DC voltage converters) especially for time-based analog-to-digital converters (T-ADCs). In T-ADCs, the input voltage signal is first converted into a delay pulse using the VTC circuit, then this delay signal is converted into a digital code...
The performance limitations of the single cell FAMOS transistor have hindered the development of high speed MOS EPROM's that can match Bipolar PROMs for speed. Previous approaches to high speed MOS EPROMS have centered around a 4-T 11 I or a 2-T cell with It's inherent die area disadvantage and, hence, resulted in their manufacturable densities being limited to under 64K.
This paper analyzes the single event transient (SET) response of a single event latchup (SEL) protection switch (SPS) designed in the 130 and 250 nm bulk CMOS technologies. The analysis has been conducted through the SPICE simulations, using the standard double exponential current source as the SET model. It has been confirmed that the 130 nm SPS cell is more susceptible to SETs than the 250 nm version,...
In this paper, we analyze the impact of voltage, temperature and body-biasing on the detection of resistive short defects for low-VT (LVT) and regular-VT (RVT) configurations of a 28nm UTBB FDSOI (Ultra Thin Body & BOX Fully Depleted Silicon-On-Insulator) technology. We implemented a similar design in each configuration and compared their electrical behaviors with the same resistive short...
In this paper, a low power 5-bit hybrid flasharchitecture is proposed. The proposed analog-to-digital con-verter (ADC) uses appropriate combination of both conventionaldouble-tail comparators and standard cell comparators. Stan-dard cell comparators are used to reduce power consumption. Thus, the proposed hybrid architecture results in extendeddynamic range when compared to standard cell and thresholdinverter...
Nowadays, the security of chip is getting more important. The research of hardware Trojans, which is closely related with the security of the chip, is becoming a new research hotspot. In this paper, based on the main technology of chip manufacturing and the latch up effect of CMOS process, a physical destruction hardware Trojan based on the latch up effect is designed. In the activation of the hardware...
This A fundamental memory unit in traditional computers is typically constituted by several MOSFETs. For biological systems, it is uneasy to realize such a unit for data memorization. How to synthesize a specific storage unit is a preliminary but an important step toward the success of future bio-computers. This paper proposes a structure of a fundamental memory unit necessary with I/O configuration...
Power electronic converters, next to PV panels, are an important element of PV systems. They are responsible for converting electrical energy parameters such as: voltage, current and frequency values. This paper presents a detail performance analyze and simulation studies of small photovoltaic energy system. The proposed system consist: a step-up converter fed from the PV array, a high-frequency transformer,...
Absolute value comparators are becoming essential building blocks for new biomedical signal processing systems. Direct conversion of conventional comparators, which work on actual signal values, into absolute value comparators involve full wave rectifiers and this is suboptimal for a number of reasons. This paper presents a novel absolute value comparator circuit implemented without the use of full-wave...
This paper presents a low-voltage latch current comparator. The circuit was designed on the basis of current mirror, preamplifier and latch circuits and also various circuit techniques; quasi-floating gate to reduce the input impedance, bulk driven technique for the circuit to be operable under low supply voltage and positive feedback to increase the gain and the overall speed. From the simulation...
This paper presents a Mach-Zehnder-based transmitter in 0.18 µm CMOS. An asymmetric driver is proposed to achieve a large output swing on the optical modulator. The logical effort method was applied on each driver block in order to optimize the propagation delay. The driver characteristics are analyzed based on slew-rate limitation. The speed-power-area trade-off is highlighted and enables to adjust...
The desaturation and charge recovery behavior for 1200-V RC-IGBTs with diode control is investigated. The low thickness of the drift-region of modern 1200-V IGBTs results in significantly reduced time constants of the diode-control feature. While a low desaturation time constant is well acceptable, the recovery time constant becomes critical when compared to typical locking time requirements of common...
This work presents SAEDE (Statistically-Aided Electronic Design Environment), a framework targeted to perform advanced statistical analysis within an ASIC design workflow, linking together circuit performance with technological parameters. A driving example, the design of a 10-stage delay line, is conducted. The study goals are two-fold: extract a circuit performance metric, the spread of the stage-delay,...
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